End-to-end SpinalHDL skill for generating, reviewing, explaining, and validating RTL (Scala HDL). Covers DSL semantics (`:=`, `<>`, `Reg`, `Stream`, `Flow`, `Bundle`, `Vec`, `ClockDomain`, `StateMachine`, `Mem`, `BusSlaveFactory`), pipeline and plugin composition (`spinal.lib.misc.pipeline`, `spinal.lib.misc.plugin`), simulation with `SimConfig`/`doSim`, and architecture patterns drawn from official SpinalHDL docs and VexRiscv. Load for SpinalHDL DSL questions, module implementation, interface design, SoC integration, bug hunting, error-message decoding, and simulation or build validation.
2026-05-20