// Adds an ngspice-backed simulation testbench to a Zener `.zen` design. Use when the user asks to simulate a circuit, validate behavior in SPICE, or wire a `spice_model=SpiceModel(...)` into a leaf component. Covers `pcb sim`, `Simulation` property, and ngspice `.control` blocks with `tran`/`PULSE`/`PWL` sources and SVG `hardcopy` output.
Use before creating or modifying reusable PCB registry content, including component packages, symbols, footprints, STEP models, datasheets, or reusable Zener modules. Also use when working inside a registry component package or changing KiCad/Zener files that define reusable parts. Covers search-before-authoring, datasheet-backed cleanup, package structure, sourcing checks, and validation.
Canonical Zener HDL semantics and workflow. Use before reading or modifying `.zen` files. Covers module loading and instantiation, `io()`/`config()` API design, nets/interfaces/power domains, components and sourcing, `pcb.toml` manifests, stdlib/package discovery with `pcb doc`, physical units, generics, checks, DNP patterns, naming, and validation.
Search the registry for prepared Zener modules, reference designs, and component symbols while designing a board, subsystem, or spec. Use for board-facing part/module selection with `pcb search -m registry:modules` and `pcb search -m registry:components`, API inspection, sourcing comparison, and deciding what to instantiate. If no suitable registry package exists, prepare a librarian request instead of importing or authoring components inline.
Read datasheets and technical PDF documents with `pcb scan`. Use when the user gives a local PDF path or an `http(s)` datasheet/document URL, when a task requires reading, summarizing, extracting information from, or answering questions about a datasheet or technical PDF, or when a KiCad symbol / `.kicad_sym` provides a `Datasheet` property to resolve. Run `pcb scan <input>` in bash, treat stdout as the generated `.md` path, then read that markdown file.
| name | spice-sim |
| description | Adds an ngspice-backed simulation testbench to a Zener `.zen` design. Use when the user asks to simulate a circuit, validate behavior in SPICE, or wire a `spice_model=SpiceModel(...)` into a leaf component. Covers `pcb sim`, `Simulation` property, and ngspice `.control` blocks with `tran`/`PULSE`/`PWL` sources and SVG `hardcopy` output. |
Add a small ngspice-backed testbench to a .zen design.
Confirm the target is simulation-capable by running a dummy sim. pcb sim <path/to/file.zen> --setup "* empty setup check"
If the SPICE model is missing, add it.
Find a vendor model, download it, or create a simple behavioral model if needed. Wire it through the leaf component with spice_model=SpiceModel(...) before writing the testbench.
Create a focused testbench file.
Use a generic package-local path such as <package>/testbench/test_<scenario>.zen.
Keep the structure simple:
Simulation(...) blockSimulation.setup.
Use raw ngspice for:DCPULSE(...)PWL(...).controltranhardcopytestbench/output/<scenario>.svg.Simulation is a Zener property loaded from @stdlib/properties.zen and attached as a normal top-level object:
load("@stdlib/properties.zen", "Simulation")
Simulation(
name="SIM",
setup="""
* raw ngspice goes here
.control
tran 10u 10m
.endc
""",
)
The setup string is passed through as ngspice input. Put voltage sources, waveform definitions, analysis commands, and plot/export commands there.
"""<Part> <scenario> simulation test."""
load("@stdlib/properties.zen", "Simulation")
Target = Module("../Target.zen")
Resistor = Module("@stdlib/generics/Resistor.zen")
VIN = Power(voltage="12V")
VOUT = Power()
GND = Ground()
Target(
name="UUT",
VIN=VIN,
VOUT=VOUT,
GND=GND,
)
Resistor(
name="R_LOAD",
value="10ohm",
package="0603",
P1=VOUT,
P2=GND,
)
Simulation(
name="SIM",
setup="""
* <Part> <scenario>
V_IN VIN GND DC 12
.control
tran 10u 10m
set hcopydevtype = svg
hardcopy output/<scenario>.svg v(VIN) v(VOUT) title "<Part> <scenario>" xlabel "Time" ylabel "Voltage"
.endc
""",
)
If the leaf component does not already expose a SPICE model, add one like this:
VIN = io(Power())
VOUT = io(Power())
GND = io(Ground())
Component(
name="MyPart",
symbol=Symbol(library="MyPart.kicad_sym"),
pins={"VIN": VIN, "VOUT": VOUT, "GND": GND},
spice_model=SpiceModel(
"MyPart.lib",
"MyPart_SUBCKT",
nets=[VIN, VOUT, GND],
args={},
),
)
Load switch enable test:
V_IN VIN GND DC 5.3
V_ON ON GND PULSE(0 0.9V 1ms 10us 10us 3ms 5ms)
Protection threshold sweep:
V_IN VIN GND PWL(0 12 5m 12 5.1m 22 10m 22 10.1m 12 15m 12 15.1m 2 20m 2)
setup.