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vivado-timing

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Atualizado22 de abril de 2026 às 23:03

Analyze and fix timing violations. Use when WNS is negative, when asked to close timing, fix setup/hold violations, analyze critical paths, or improve max frequency.

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devansh0703

devansh0703/vivaclaw-agent

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Ocupações relacionadasSOC

Baseado na classificação ocupacional SOC

Desenvolvedores de softwareInformática e Matemática·SOC 15-1252

SKILL.md

readonly

name	vivado-timing
version	1.0.0
description	Analyze and fix timing violations. Use when WNS is negative, when asked to close timing, fix setup/hold violations, analyze critical paths, or improve max frequency.
metadata	{"openclaw":{"requires":{"bins":["vivado"]},"emoji":"⏱️"}}

Vivado Timing Closure Runbook

1. Diagnostic Suite

open_checkpoint /tmp/vivaclaw_post_route.dcp
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_internal -max_paths 10 -input_pins -file /tmp/vivaclaw_rpt/timing_summary.rpt
report_design_analysis -timing -logic_level_distribution -file /tmp/vivaclaw_rpt/design_analysis.rpt

2. Path Investigation

set p [get_timing_paths -max_paths 1 -slack_lesser_than 0 -delay_type max]
if {$p != ""} {
    puts "SLACK: [get_property SLACK $p]"
    puts "LOGIC_LEVELS: [get_property LOGIC_LEVELS $p]"
    puts "DATAPATH_DELAY: [get_property DATAPATH_DELAY $p]"
}

3. Strategy Table

Condition	Action
Logic Levels > 8	Re-synth: `-directive PerformanceOptimized -retiming`
Route Delay > 60%	`route_design -directive AggressiveExplore`
Hold Violation	`phys_opt_design -directive ExploreWithHoldFix`
High Fanout (>5k)	`set_property MAX_FANOUT 100 [get_cells <driver>]`

4. Logic Level Targets (MHz vs Levels)

MHz	Max Levels
100	16
200	8
300	6
400	4

5. Directive Escalation Ladder

place=WLDrivenPlacement, route=Default
place=AltSpreadLogic_high, route=Explore
place=ExtraNetDelay_high, route=AggressiveExplore
phys_opt=AggressiveExplore, route=MoreGlobalIterations
phys_opt=AlternativeFlowWithRetiming, route=AggressiveExplore

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name	vivado-timing
version	1.0.0
description	Analyze and fix timing violations. Use when WNS is negative, when asked to close timing, fix setup/hold violations, analyze critical paths, or improve max frequency.
metadata	{"openclaw":{"requires":{"bins":["vivado"]},"emoji":"⏱️"}}

Vivado Timing Closure Runbook

1. Diagnostic Suite

open_checkpoint /tmp/vivaclaw_post_route.dcp
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_internal -max_paths 10 -input_pins -file /tmp/vivaclaw_rpt/timing_summary.rpt
report_design_analysis -timing -logic_level_distribution -file /tmp/vivaclaw_rpt/design_analysis.rpt

2. Path Investigation

set p [get_timing_paths -max_paths 1 -slack_lesser_than 0 -delay_type max]
if {$p != ""} {
    puts "SLACK: [get_property SLACK $p]"
    puts "LOGIC_LEVELS: [get_property LOGIC_LEVELS $p]"
    puts "DATAPATH_DELAY: [get_property DATAPATH_DELAY $p]"
}

3. Strategy Table

Condition	Action
Logic Levels > 8	Re-synth: `-directive PerformanceOptimized -retiming`
Route Delay > 60%	`route_design -directive AggressiveExplore`
Hold Violation	`phys_opt_design -directive ExploreWithHoldFix`
High Fanout (>5k)	`set_property MAX_FANOUT 100 [get_cells <driver>]`

4. Logic Level Targets (MHz vs Levels)

MHz	Max Levels
100	16
200	8
300	6
400	4

5. Directive Escalation Ladder

place=WLDrivenPlacement, route=Default
place=AltSpreadLogic_high, route=Explore
place=ExtraNetDelay_high, route=AggressiveExplore
phys_opt=AggressiveExplore, route=MoreGlobalIterations
phys_opt=AlternativeFlowWithRetiming, route=AggressiveExplore