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End-to-end EasyEDA Pro workflow guidance for setup, inspection, controlled writes, exports, and reporting through EasyEDA MCP Pro.
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Baseado na classificação ocupacional SOC
Plan, preview, apply, and verify professional EasyEDA Pro schematic layouts with page/title-block geometry, rendered bounds, functional blocks, relationship-aware spacing, deterministic templates, staged readback, connectivity fingerprints, and visual QA. Use for schematic placement, cleanup, fit-to-page work, or any request to make a schematic professional or readable.
Antigravity guidance for deterministic, geometry-aware professional EasyEDA schematic layout and QA.
Claude Code guidance for deterministic, geometry-aware professional EasyEDA schematic layout and QA.
Codex guidance for deterministic, geometry-aware professional EasyEDA schematic layout and QA.
End-to-end EasyEDA Pro workflow guidance for setup, inspection, controlled writes, exports, and reporting through EasyEDA MCP Pro.
EasyEDA component discovery, BOM review, LCSC/JLCPCB sourcing, pricing, availability, and part-risk workflow through EasyEDA MCP Pro.
| name | easyeda-workflow |
| description | End-to-end EasyEDA Pro workflow guidance for setup, inspection, controlled writes, exports, and reporting through EasyEDA MCP Pro. |
Use this skill when an AI agent is asked to work with an EasyEDA Pro project through EasyEDA MCP Pro.
This skill is specific to oaslananka/easyeda-mcp-pro and must stay aligned with the registered MCP tools in src/tools/ and the tool list in README.md.
Use this skill for:
Do not use this skill to bypass EasyEDA Pro, bridge-extension, tool-profile, or scope restrictions.
Collect:
stdio or http transport modeTOOL_PROFILE: core, pro, full, dev, or experimentalnot_available data (e.g. easyeda_pcb_components returns total:0 with no PCB open). If a read tool that should have data returns nothing, check tab focus before assuming the project is empty.easyeda_health_checkeasyeda_bridge_statuseasyeda_get_capabilitieseasyeda_get_server_configeasyeda_get_tool_profileseasyeda_get_feature_flagseasyeda_observability_reporteasyeda_run_self_testeasyeda_api_inventoryeasyeda_schematic_netseasyeda_schematic_componentseasyeda_schematic_net_detaileasyeda_schematic_sheet_infoeasyeda_schematic_component_pinseasyeda_schematic_validate_netlisteasyeda_schematic_verify_writeUse only after explicit permission and bridge capability confirmation.
easyeda_schematic_place_componenteasyeda_schematic_add_wireeasyeda_schematic_add_text — free-standing text label (section headers, notes); cosmetic only, not a net labeleasyeda_schematic_add_rectangle — grouping/divider box for organizing a busy schematic into labeled blocks; pair with add_text for the titleeasyeda_schematic_add_circle — decorative circle marker; cosmetic onlyeasyeda_schematic_add_polygon — closed custom shape from 3+ vertices (callouts, block-diagram elements); cosmetic onlyeasyeda_schematic_set_title_block — edit title block text fields (Company, Version, Drawn, Reviewed, Page Size) only. Do not attempt to widen this tool to other title-block fields (Symbol, Border, Device, Name, Description, Width/Height, Region*, "@"-prefixed, ID): a past attempt to round-trip the full snapshot corrupted a real project's title block (EasyEDA Pro's own Log panel flagged "abnormal data" on the Symbol/Device property) — those fields are read-only through this native API, either silently ignored or throwing a native TypeError, and are only fixable via the EasyEDA Pro UIeasyeda_schematic_create_net_flageasyeda_schematic_create_net_porteasyeda_schematic_connect_pin_to_neteasyeda_schematic_connect_pins_by_neteasyeda_schematic_modify_primitiveeasyeda_schematic_delete_primitiveeasyeda_schematic_sync_to_pcbeasyeda_project_saveConnectivity model: wires/stubs sharing the same netName merge into one net regardless of physical location or distance — prefer connect_pin_to_net/named stubs over drawing a continuous route when the goal is just correct connectivity, not a hand-routed look. The collision guard (NET_COLLISION) only catches a foreign net at an exact touched coordinate (a wire/pin/flag endpoint) — it does not catch a wire whose interior merely crosses a foreign point. EasyEDA also rejects diagonal (non-axis-aligned) wire segments outright; keep routing to horizontal/vertical only.
easyeda_schematic_sync_to_pcb is not fire-and-forget. It is the only way to get a schematic-placed part (addIntoPcb: true) onto the linked PCB — easyeda_pcb_place_component's direct create is confirmed broken (see PCB write workflow note below) — but calling it only opens a confirmation dialog in EasyEDA Pro's UI; the tool call itself returns success immediately regardless of what happens next. A human must click through that dialog before the part actually appears on the board. Always verify with easyeda_pcb_components after asking the user to approve the dialog — never report a PCB sync as complete based on the tool's return value alone.
easyeda_board_layerseasyeda_board_stackupeasyeda_board_dimensionseasyeda_board_featureseasyeda_pcb_constraint_checkeasyeda_pcb_constraint_reporteasyeda_pcb_production_reviewUse only after explicit permission and bridge capability confirmation.
easyeda_pcb_place_component_groupeasyeda_pcb_route_path_planeasyeda_pcb_place_component — confirmed broken: the native PCB_PrimitiveComponent.create() call this wraps never resolves. Do not use it to get a new part onto the board. The real path is schematic-side: place the part with easyeda_schematic_place_component (addIntoPcb: true, the default), then easyeda_schematic_sync_to_pcb (see schematic write workflow above for its human-in-the-loop caveat). Once the part exists on the PCB this way, easyeda_pcb_modify_component correctly repositions/rotates it.easyeda_pcb_add_trackeasyeda_pcb_add_viaeasyeda_pcb_add_zone — confirmed broken: the native PCB_PrimitivePour.create() call never resolves. No working alternative exists (unlike component placement, copper pours are not a schematic concept, so there is no sync-based workaround). Report this as an unsupported capability rather than attempting it.easyeda_pcb_add_text — silkscreen/label text on a PCB layer (typically Top/Bottom Silkscreen, layer id 3/4); fontFamily must be a name the runtime's font list contains — the default NotoSansMonoCJKsc-Regular is live-verified to workeasyeda_pcb_add_silkscreen_line — non-electrical decorative line (section dividers, board art); reuses the same primitive as add_track but with an empty net name so it never appears in the netlist/ratsnesteasyeda_pcb_modify_componenteasyeda_pcb_delete_componenteasyeda_project_saveeasyeda_live_write_regression — exercises real schematic and/or PCB write paths (place/connect/wire/delete, via/track/list/delete) against the connected bridge in one call and reports pass/fail per step, self-cleaning afterward. Useful to sanity-check the bridge/extension itself before trusting a larger write workflow, or to reproduce a suspected regression. Requires testDeviceItem (resolve one via easyeda_schematic_search_device first) and the matching tab focused per scope.easyeda_canvas_captureeasyeda_canvas_capture_regioneasyeda_canvas_locateeasyeda_export_gerberseasyeda_export_pick_placeeasyeda_export_pdfeasyeda_export_netlisteasyeda_production_qa_artifactseasyeda_jlcpcb_quote_workfloweasyeda_health_check, easyeda_bridge_status, and easyeda_get_capabilities.easyeda_get_tool_profiles and easyeda_get_feature_flags.easyeda_api_call.easyeda_project_save.A complete EasyEDA workflow response must include:
Stop and report clearly when:
not_available result where data was expected — check document tab focus before concluding the project is emptyeasyeda_pcb_place_component or easyeda_pcb_add_zone is requested directly — redirect to the working alternative (or report no alternative, for zones) instead of attempting the broken callReturn:
Do not claim an EasyEDA project is manufacturing-ready based only on write success. Manufacturing readiness requires validation, export review, and qualified human approval.