oniondas

Build, explore, and verify Verilog/SystemVerilog RTL. Use when the user wants to write an RTL module, understand or review existing Verilog, or verify a design against a Python golden model with cocotb. Also extracts and diagrams control FSMs from the AST (deterministic, no hallucinated states) when a state diagram is explicitly wanted — but default to writing or reading Verilog, not diagramming.