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SkillsMP 已收集 Arcadia-1/analog-agents 中的 15 个 Skill。打开任一 Skill 可查看来源和详情。
已展示 15 / 15 个已收集 Skill。
Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have…
原文语言：英语
ADC characterization orchestrator in the analog-agents project. Takes simulated/measured ADC output, produces the standard specs bundle (SNDR/SFDR/THD/ENOB, INL/DNL, FOM, NTF where applicable) as a verifier-report, and hands off back to the design/sizing…
原文语言：英语
Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.
原文语言：英语
Move, clone, package, archive, split, or reorganize Cadence Virtuoso cells and libraries at the design-data level. Use this skill whenever the user wants to: copy a TB to another library, reproduce a sim independently in a fresh library, hand off a design,…
原文语言：英语
Self-evolution engine for analog-agents. Reviews completed design sessions to extract lessons, discover new anti-patterns, propose checklist additions, and refine agent prompts. Run after design convergence or project completion. TRIGGER on: "evolve", "what…
原文语言：英语
MANDATORY — MUST load this skill when the user mentions: OTA, ADC, PLL, comparator, bandgap, LDO, amplifier, opamp, or any analog/mixed-signal IC design task. Full analog design pipeline: spec -> architecture -> design -> verify -> deliver. Orchestrates…
原文语言：英语
Audit analog circuit netlists for correctness, quality, and risks. Supports both pre-layout (schematic) and post-layout (extracted) netlists. Post-layout mode filters massive parasitic netlists before auditing. Works without EDA. TRIGGER on: "audit", "review…
原文语言：英语
Explore analog design space without simulation. Compare topologies, sweep parameters with hand calculations, find theoretical limits and Pareto tradeoffs. Use for architecture selection, initial sizing, or understanding design space before committing to EDA…
原文语言：英语
Interactive analog design learning companion. Explains circuit design decisions step by step with underlying physics. Use when learning analog design, studying a topology, or wanting detailed explanations of design tradeoffs. TRIGGER on: "teach me",…
原文语言：英语
Cross-model circuit design review with divergence analysis. Sends netlist and rationale to multiple external LLMs for independent audit. Supports minimax-m2.7, qwen-3.6-plus, kimi-k2.5, glm-5.1. Use after analog-design to get independent review before…
原文语言：英语
Transistor-level circuit design for one analog sub-block. Produces Spectre netlist with hand-calculation rationale. Use when designing a specific circuit block after architecture is defined.
原文语言：英语
Knowledge graph for analog circuit design. Stores topologies, strategies, corner lessons, anti-patterns, and project cases. Query with consult, add entries, track relationships, archive project cases. Use to build and query design knowledge across projects.
原文语言：英语
Architect Phase 1: decompose top-level analog spec into sub-block specs. Use when starting a new analog design to select architecture, allocate budgets, define sub-block specs, write testbenches, and create verification plans.
原文语言：英语
Architect Phase 3: replace behavioral models with verified transistor netlists and run top-level integration verification. Use after all sub-blocks pass L2.
原文语言：英语
Architect Phase 2: build Verilog-A behavioral models and validate system architecture. Use after analog-decompose to verify top-level specs are achievable before transistor design.
原文语言：英语