菜单
Distil append-only experiences.jsonl run records into per-domain knowledge.md summaries for the analog design agents. Use after enough runs accumulate to merge new convergence fixes, sizing recipes, PDK quirks, and tool flags into the Tier-2 knowledge file.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Analog circuit (schematic) design — topology selection, device sizing via gm/Id, biasing, schematic capture, pre-layout ERC, and design review. Use when designing an op-amp, comparator, bandgap, LDO, bias generator, or any analog block from a block specification through to a sign-off-ready schematic and netlist.
EDA tool detection, wrapper deployment, and MCP configuration for analog/mixed-signal + RF design environments. Use when setting up a workstation, verifying tool availability before a domain flow, or generating per-tool install scripts with TCL modulefiles.
Floorplan, generate matched devices, and place/route analog blocks with symmetry, shielding, and matching constraints to a clean, DRC-ready layout. Use when turning a sign-off-ready schematic into a GDS layout, or servicing a fix_request that repairs the layout after a DRC/LVS or parasitic-degradation failure.
Run DRC, LVS, antenna/ERC, and density/DFM checks on an analog layout and sign off a physically-clean GDS. Use when verifying a custom layout against the foundry rule deck and the source netlist, or re-validating after a custom-layout fix_request was serviced. Opens fix_requests routed to custom-layout on DRC/LVS failures.
Cross-domain loop orchestration for the analog/mixed-signal + RF design pipeline. Provides the fix_request protocol, iteration-cap logic, the authoritative design_state.json constraints schema, failure classification, and approval checkpoints. Use when driving the closed-loop spec↔circuit↔layout feedback cycle.
Solve the electromagnetics of an on-chip passive or antenna (inductor, transformer, transmission line, balun, antenna), extract a converged passive S-parameter model, and fit a lumped equivalent for circuit-level RF simulation. Use when building the passive model rf-design consumes, or to service an rf-design fix_request (route_to: em-modeling) by re-solving the passive. Loop-backs are stage-local (passivity/fit → meshing/geometry_definition); passivity is a hard gate; a fundamental geometry/stackup gap escalates.
| name | memory-keeper |
| description | Distil append-only experiences.jsonl run records into per-domain knowledge.md summaries for the analog design agents. Use after enough runs accumulate to merge new convergence fixes, sizing recipes, PDK quirks, and tool flags into the Tier-2 knowledge file. |
| version | 1.0.0 |
| author | chuanseng-ng |
| license | MIT |
| allowed-tools | Read, Write, Bash |
Invoke as /analog-design-infrastructure:memory-keeper --domain <domain> (or --all).
This skill runs the distillation helper, reviews the candidate patterns, and updates the
relevant <domain>/knowledge.md under the resolved memory root — it does not spawn an
orchestrator. Pass --init (runs memory_root.py --init) to resolve and seed the central
memory root and migrate any repo-local runtime data, without distilling.
Memory does not live at a fixed relative memory/ path. The active root is resolved by
memory_root.py (the single source of truth that distill.py and tools/qor_trends.py import),
in this priority order:
--memory-root PATH argument$CHIP_DESIGN_MEMORY_ROOT environment variable${XDG_DATA_HOME:-$HOME/.local/share}/chip-design-agents/analog/memory
(Windows: %LOCALAPPDATA%\chip-design-agents\analog\memory)memory/ tree as a seed fallback (used only if the central root is unwritable)The in-repo memory/ tree is the version-controlled seed: on first resolution each
<domain>/knowledge.md is copied into the central root if absent (never overwriting accumulated
data; runtime experiences.jsonl/run_state.md are never seeded). Orchestrators resolve this same
root at session start and use it as <MEM> for every read/write. Print it with
python3 plugins/infrastructure/skills/memory-keeper/memory_root.py (add --init to seed +
migrate + report). Per-project scoping: export CHIP_DESIGN_MEMORY_ROOT="$PWD/memory".
Read the Tier-1 memory/<domain>/experiences.jsonl run records, identify new issue/fix
patterns and tool flags not already captured, and update the Tier-2
memory/<domain>/knowledge.md summaries without discarding still-valid content. This keeps
the knowledge each orchestrator reads at session start current as experience accumulates.
python3 distill.py <domain> [--min-records N] [--memory-root PATH].
It emits a JSON summary (issue/fix pairs, tool-flag candidates, metric ranges, signoff
rate) and exits with code 2 (skip) when fewer than --min-records records exist
(default threshold: 5).distill.py VALID_DOMAINS (the 14 design domains plus
infrastructure and meta). Each has a numeric key_metrics field set in METRIC_FIELDS.knowledge.md; preserve still-valid existing content. De-duplicate near-identical entries.experiences.jsonl — it is the append-only source of truth.knowledge.md sections updated without loss of still-valid content| Issue | Fix |
|---|---|
Fewer than --min-records records | Skip (exit 2); re-run after more runs accumulate |
| Malformed JSONL line | Helper warns and skips the line; fix the producer if recurring |
memory/<domain>/knowledge.md (merged, not overwritten)