dev-guide

Guides behavior model ↔ RTL equivalence checking — sampling point selection (commit/retire vs transaction-edge vs cycle), drive direction (DUT pushes ref), DPI-C probe interface, async event alignment, snapshot-based debugging, and DSL-driven probe generation. Activate when the user explicitly invokes /chipdev-method:align-and-difftest, or asks "怎么 diff cmodel 和 RTL", "behavior 对不上 RTL", "difftest 怎么搭", "what should I sample", "RVVI vs DPI", or "snapshot for difftest", or sets up a difftest infrastructure.

Routes a methodology compliance review of the user's current changes to Codex via the codex-plugin-cc adversarial-review command. Activate when the user explicitly invokes /chipdev-method:audit, or asks "audit my diff", "审一下我这版改动", "review my methodology compliance", "did I violate any of the principles", or wants an independent adversarial check that their work follows the plugin's six invariants and contract-first discipline.

Guides the construction of a functional behavior model that decouples timing but preserves architectural state for RTL difftest — what to keep, what to drop, where to embed probes, how to package the cross-language interface, and how to coordinate memory with the DUT. Activate when the user explicitly invokes /chipdev-method:build-behavior-model, or asks "什么是行为模型", "behavior model 边界", "difftest 用什么 ref 模型", "怎么做 functional simulator", or designs the reference half of a difftest setup.

Guides the construction of a cycle-accurate performance model — scheduler model, module lifecycle, idle/advance contract, pipeline primitives, sparse memory, transaction memory pool, configuration system, and dump infrastructure. Activate when the user explicitly invokes /chipdev-method:build-perf-model, or asks "怎么写 cycle-accurate 模拟器", "性能模拟器怎么写", "how to model timing", "should I use SC_THREAD or advance loop", or is implementing a microarchitecture timing model.

Guides RTL frontend design discipline — module boundary rules, synthesizability constraints, observability instrumentation, lint cleanliness as a hard gate, reset strategy, and clock-domain crossing. Activate when the user explicitly invokes /chipdev-method:build-rtl, or asks "RTL 怎么分层", "should I use always_ff or always", "怎么做 lint clean", "reset strategy", "CDC how to handle", or starts writing SystemVerilog for a new module.

Helps the user decide whether to build a performance model, a behavior model, or RTL for a chip frontend task, and in what order. Activate when the user explicitly invokes /chipdev-method:choose-artifact, or asks variants like "should I write cmodel or RTL first", "怎么选模型", "what artifact do I need", or stands at the start of a new chip / module / subsystem and has not yet committed to an artifact path.

Designs the contracts that hold across performance model, behavior model, and RTL — single-source-of-truth interface DSL, hierarchy DSL, global constants, protocol annotations, state contracts, observability hooks, and alignment points. Activate when the user explicitly invokes /chipdev-method:define-contracts, or when they describe defining new module boundaries, designing an interface DSL, planning difftest probes, asking "怎么定义接口", "interface DSL", "single source of truth", or starting any chip frontend project that will have more than one artifact.

Routes a build, simulation, test, or difftest failure to Codex via the codex-plugin-cc rescue command for root-cause investigation. Activate when the user explicitly invokes /chipdev-method:diagnose, or describes a failure ("build failed", "sim hangs", "difftest mismatch on cycle X", "loss went NaN", "OOM at step Y", "为什么挂了", "为什么对不上") and wants an independent investigation, or has been staring at a stack trace / log / waveform without progress.