菜单
Analyze FSDB waveforms, debug simulation errors, explore netlist hierarchy, or run Verdi VIA apps in batch mode.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Generate a minimal blackbox/empty placeholder module (.empty.v) for a DUT by sampling its output port default values from a ksim FSDB waveform. Use when a DUT needs to be replaced by a stub (e.g., a CPU, accelerator, or DSP replaced by a non-functional placeholder) for SoC-level testing. The skill is DUT-agnostic: it works with any SystemVerilog/Verilog module whose FSDB waveform is available.
Generate uvm register-model companion headers (C .h for BSP and SystemVerilog .svh for testbench) from a Synopsys DesignWare IP databook text extract. Use when you need to produce project-convention RegDef.h/RegDef.svh files that match the layout used by `dv/simulation/verif_env/soc/header_files/` (one typedef-union per register, per-register offset + addr macros). The skill is IP-agnostic across Synopsys IP families (DW_apb_*, DW_axi_*, DWC_*) provided the input text uses the standard 'N.M.K REG_NAME' section markers and 'Table N-M Fields for Register: NAME' field tables.
Use when the user needs to analyze a design specification (PDF/document) and RTL source to extract verification-relevant information and produce a structured testplan. Covers： spec analysis, FSM extraction, register encoding analysis, and testplan generation. This is the first stage of a UVM verification pipeline -no EDA tools required.
Use when the user needs to generate UVM test cases and virtual sequences from a testplan. Produces test classes, virtual sequences, and updates testname.f. Each test follows the standard factory-registered pattern with raise/drop objection. Code generation only -compilation and simulation verification is Stage 5.
| name | fsdb-analysis |
| description | Analyze FSDB waveforms, debug simulation errors, explore netlist hierarchy, or run Verdi VIA apps in batch mode. |
| metadata | {"author":"康耀鹏","organization":"personal","contact":"78490223@qq.com"} |
Synopsys Verdi VIA (Verdi Interoperable Apps) for FSDB waveform analysis and netlist exploration. Tcl-based apps with Perl batch wrappers + C++ NPI plugins.
export VERDI_HOME=/eda_tools/synopsys/verdi/W-2024.09-SP1
export PATH="$VERDI_HOME/bin:$PATH"
# Optional: export VCS_HOME=/path/to/vcs # for Coverage UCAPI
cd $PROJ_HOME/.claude/skills/fsdb-analysis/scripts
# design.f based
./Bin/<app>.pl -f <design.f> -o <output.log> [options]
# DBDIR based
./Bin/<app>.pl -dbdir <simv.daidir> -o <output.log> [options]
# Get help
./Bin/<app>.pl -help
Waveform/FSDB: fsdbSigQ.pl, getRegValues.pl, npiFsdbFreqDuty, wi_merge_fsdb.pl, custom Tcl via $VERDI_HOME/bin/novas -play <script.tcl> -batch
Netlist: getModHier.pl, getModIO.pl, getConstAssign.pl, findInst.pl
Design checks: detectDanglingPort.pl, detectPortZ.pl, detectConstPort.pl
references/architecture.md — three modes (Tcl Apps / Perl Batch / C++ NPI), RC config systemreferences/tools.md — all tools by category (DesignComprehension / Validation / Manipulation / FsdbInvestigation)references/fsdb_api.md — NPI FSDB API cheat sheet, built-in FSDB batch tools, custom Tcl script templatereferences/troubleshooting.md — Tcl pitfalls, file naming conventions, C++ plugin build guide