菜单
Generate KiCad schematics from a Circuit Weaver design.yaml or a project's own checked-in generator. Use for large, repetitive, or machine-synchronized designs. Prefer the Circuit Weaver CLI unless the project actually contains and documents its own generation scripts.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Create, import, analyze, or resume an end-to-end Circuit Weaver electronic design with durable project state. Load the canonical workflow from skills/circuit-weaver/SKILL.md. Use kicad for one-off file inspection, bom for sourcing, and design-wizard only when explicitly requested.
Use only for an explicitly requested step-by-step Circuit Weaver questionnaire. Load the canonical workflow from skills/design-wizard/SKILL.md; use circuit-weaver for ordinary automatic new-design requests.
Route non-critical nets on a real KiCad PCB or Specctra DSN through Circuit Weaver's fail-closed Freerouting integration. Use after placement and net-class setup when the user requests autorouting, a validated SES session, routing diagnostics, or post-route cleanup. Keep critical power, RF, clock, crystal, switching, and differential nets manual.
Design and verify professional multi-sheet KiCad hierarchies generated from Circuit Weaver functional sections. Use when adding, splitting, renaming, or reviewing schematic sheets, cross-sheet interfaces, root symbols, sheet ownership, or final hierarchy ERC.
Review Circuit Weaver's exhaustive placement proposal and apply approved SVG coordinates to a real electrically annotated KiCad PCB. Use after schematic generation for placement optimization, official-reference review, interactive SVG editing, strict reference reconciliation, and PCB placement handoff. Do not treat review artifacts as fabrication data.
Pin-to-net mapping auditor -- verifies that every IC pin in the schematic is connected to the correct net, matched against a pin map source of truth (CSV, datasheet table, or Python dict). Critical for BGA/QFN devices where swap errors are invisible to DRC/ERC.
| name | kicad-gen |
| description | Generate KiCad schematics from a Circuit Weaver design.yaml or a project's own checked-in generator. Use for large, repetitive, or machine-synchronized designs. Prefer the Circuit Weaver CLI unless the project actually contains and documents its own generation scripts. |
1. Define components and pin maps in design.yaml
2. Generate sheets -> circuit-weaver generate
3. Require real ERC -> circuit-weaver generate --require-kicad
4. Review in KiCad -> open .kicad_sch files, run Update PCB from Schematic
Give each block a stable unique id and functional section. Circuit Weaver
preserves explicit sections as separate sheets, keeps generated support parts
with their owning block, and disambiguates sanitized sheet filenames. Read the
root and child paths from artifact_manifest.json; never guess main.kicad_sch.
Spec: ${SPEC_PATH}
Output directory: ${OUTPUT_DIR}
If a project supplies custom scripts, record their checked-in paths here. Do not
invoke scripts/generate_schematics.py or scripts/pin_maps.py unless those
files exist in the current project.
Edit this file to record:
_0_1/_1_1 sub-units REQUIRED -- SnapEDA flat format fails silently without themlib_id in schematic instances: bare names (no library: prefix)lib_id (e.g. "VCC" not "power:VCC"), (power) flag requiredround(val / 1.27) * 1.2720231120 (KiCad 8+) for per-symbol instances blocks# Transactionally regenerate and require the exact final hierarchy to pass a
# real installed kicad-cli ERC run.
circuit-weaver generate "${SPEC_PATH}" --output "${OUTPUT_DIR}" --require-kicad
# Then in KiCad GUI: Tools -> Update PCB from Schematic
Read valid, kicad_verified, verification_status, and erc from
artifact_manifest.json. Internal validation alone is not real KiCad
verification. If --require-kicad cannot run or ERC fails, generation fails;
do not claim release-quality artifacts.
Never hand-edit generated .kicad_sch files -- changes will be overwritten on next generation.
| IC | Total pins | Mapped | No-connect | Coverage |
|---|---|---|---|---|
| (fill in) |
Silent connection failure: Labels placed directly on pin endpoints without a wire stub. Fix: generate wire + label pairs, not label-only.
PCB import failure: Version mismatch -- KiCad 7 expects root-level symbol_instances;
KiCad 8+ uses per-symbol instances blocks. Use version 20231120 for KiCad 8+ compatibility.
Symbol not recognized: SnapEDA flat format lacks _0_1/_1_1 sub-unit notation.
Rebuild the symbol from scratch using the KiCad S-expression format.