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svlinter

星标2
分支1
更新时间2026年3月10日 02:46

Use this skill whenever the user wants to lint, analyze, or check SystemVerilog (.sv) design files. Triggers include: any mention of 'SystemVerilog lint', 'SV lint', 'svlinter', 'check RTL', 'check design', 'AST dump', or requests to find errors/warnings in hardware designs. Also use when filtering or querying design instances/modules, dumping syntax trees, or running diagnostics on Verilog/SystemVerilog source files. If the user asks to 'lint my design', 'check my SV files', 'find errors in RTL', or wants to analyze module hierarchies, use this skill.

安装

用 Codex 或 Claude 帮你安装 复制这段 Prompt,粘贴到 Codex、Claude 或其他助手里,让它检查 Skill 页面并帮你完成安装。

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