菜单
Run comprehensive JLCPCB DFM validation — drill rules, edge clearances, copper checks, NPTH, silkscreen, gerber completeness, and best practices. Use after PCB changes, before JLCPCB upload, or when investigating manufacturing rejections.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Full PCB verification loop using local kicad-cli (DRC + 3D render + gerbers)
Create a new Claude Code skill for this project. Use when you need to add a new skill, improve an existing skill, or convert a workflow into a reusable skill.
Verifies that every PCB pad-to-net assignment matches the manufacturer datasheet pin specifications. Use when changing board.py/routing.py/footprints.py, after GPIO remapping, before releases, or when adding new components. Automated guard against wiring errors like unconnected VBUS, wrong pin assignments, or missing GND connections.
Design intent adversary — cross-checks GPIO, nets, power chains, signal paths across firmware/schematic/PCB/datasheet sources to find lost connections and inconsistencies
Analyze a DFM report and fix all issues in the PCB generation scripts
Run DFM guard tests and add new regression tests after fixing PCB issues
| name | jlcpcb-validate |
| model | claude-opus-4-7 |
| description | Run comprehensive JLCPCB DFM validation — drill rules, edge clearances, copper checks, NPTH, silkscreen, gerber completeness, and best practices. Use after PCB changes, before JLCPCB upload, or when investigating manufacturing rejections. |
| disable-model-invocation | true |
| allowed-tools | Bash, Read, Grep, Glob |
Comprehensive manufacturing rule validation against JLCPCB capabilities.
Complements /verify (88 DFM + 9 DFA tests) with additional JLCPCB-specific checks.
/verify passes — this is an additional validation layerdfm-reference.md)cd /Users/pierrejonnycau/Documents/WORKS/esp32-emu-turbo
python3 scripts/validate_jlcpcb.py
python3 scripts/verify_dfm_v2.py && python3 scripts/verify_dfa.py
The validation covers 20+ checks in 6 categories:
| Category | Tests | What it checks |
|---|---|---|
| Drill & Hole Rules | 8 | Drill increment (0.05mm), PTH/NPTH min/max, via aspect ratio, PTH annular ring |
| Board & Edge Rules | 3 | Outline closure, copper-to-edge (0.3mm), SMD-to-edge (0.3mm) |
| Copper & Trace Rules | 2 | Copper sliver detection (< 0.1mm), power trace width |
| NPTH & Mounting Rules | 3 | NPTH-to-copper clearance, paste on NPTH, mounting hole zones |
| Silkscreen & Mask | 1 | Character height >= 1.0mm |
| Gerber & Manufacturing | 1 | All 7 required layers present |
| Best Practices | 2+ | Decoupling cap distance, fine-pitch pad width |
dfm-reference.md for JLCPCB limitsscripts/generate_pcb/)python3 -m scripts.generate_pcb hardware/kicadpython3 scripts/validate_jlcpcb.pyFor maximum confidence before JLCPCB upload, run all three:
python3 scripts/verify_dfm_v2.py && \
python3 scripts/verify_dfa.py && \
python3 scripts/validate_jlcpcb.py
All three must pass with 0 failures.
scripts/validate_jlcpcb.py — This validation script (source of truth).claude/skills/dfm-fix/dfm-reference.md — Comprehensive JLCPCB DFM rules referencescripts/verify_dfm_v2.py — Primary DFM test suite (88 tests)scripts/verify_dfa.py — DFA assembly tests (9 tests)scripts/pcb_cache.py — Shared PCB parse cacheTrace width: 0.127mm (5 mil) Via drill (2L): 0.3mm (0.2mm +$)
Trace spacing: 0.127mm (5 mil) Via pad (2L): 0.6mm (0.45mm OK)
Annular ring: 0.075mm (abs min) PTH drill: 0.15-6.3mm
Mask bridge: 0.1mm (multilayer) NPTH drill: 0.5-6.3mm
Cu to edge: 0.3mm Aspect ratio: 10:1 max
Trace to edge: 0.2mm Drill increment: 0.05mm