菜单
Use for adapting a QEMU TCG host backend, including optional op support, constraints, register allocation, host code emission, qemu_ld/st, atomics, and vector ops. Extends qemu-plan and qemu-rlcr-loop.
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基于 SOC 职业分类
| name | qemu-workflow-tcg-backend-adaptation |
| description | Use for adapting a QEMU TCG host backend, including optional op support, constraints, register allocation, host code emission, qemu_ld/st, atomics, and vector ops. Extends qemu-plan and qemu-rlcr-loop. |
Use this domain skill for host backend work under tcg/<host>/: instruction encoders, TCG_TARGET_HAS_*, constraints, tcg_out_op, qemu load/store paths, vector emission, and generated host-code bugs.
qemu-plan..oh-my-qemu/<task-slug>/.qemu-rlcr-loop and keep
implementation/debugging inside RLCR rounds.qemu-build for host backend builds.qemu-debug for TCG logs and one-insn-per-tb.qemu-model-verification for final evidence.Do not produce source code intended for QEMU upstream submission. Do not add DCO or review trailers.
A backend change is correct only when these agree:
include/tcg/tcg-opc.h and docs/devel/tcg-ops.rst;tcg-target-has.h;tcg-target-con-str.h and tcg-target-con-set.h;tcg-target.h;tcg_out_op, vector emission, or qemu_ld/st implementation in tcg-target.c.inc;Do not enable TCG_TARGET_HAS_* before constraints and emission support are complete.
Record one category in the plan:
Check:
Keep code generation paths allocation-free and simple.
Verify separately:
MemOp size, sign, and endianness;For vectors, verify:
v64/v128/v256 and specific op flags;tcg_can_emit_vec_op() / tcg_expand_vec_op() behavior.tests/tcg when available.one-insn-per-tb when frontend/backend attribution is unclear.docs/devel/code-provenance.rst.docs/devel/tcg-ops.rst.docs/devel/tcg.rst.tcg/aarch64/, tcg/riscv64/, tcg/loongarch64/.include/tcg/tcg.h, include/tcg/tcg-opc.h, include/tcg/tcg-op-common.h.Use as the first step for any non-trivial QEMU task. Produces a small implementation or debugging plan under a .oh-my-qemu task workspace with acceptance criteria, scope boundaries, artifact policy, and verification gates.
Use for QEMU board, SoC, machine, memory map, boot path, FDT/ACPI, and IRQ topology modeling. Extends qemu-plan and qemu-rlcr-loop; board work must add or extend qemu-qtest coverage for verification.
Use for booting Linux in QEMU through either direct kernel loading or firmware and bootloader stages, selecting the path from task inputs while preserving provenance, boot logs, debug handoff, and verification evidence.
Use for QEMU peripheral, accelerator, MMIO, qdev, or SysBusDevice modeling. Extends qemu-plan and qemu-rlcr-loop; register-bank modeling must use QEMU's registerinfo framework and qtest verification.
Use for adding, reviewing, or debugging a guest ISA instruction in a QEMU TCG frontend. Extends qemu-plan and qemu-rlcr-loop; this skill only defines frontend decode/translation decisions.
Use as a QEMU flow primitive to summarize sanitized oh-my-qemu agent workflow feedback, draft improvement proposals, and file them with gh when approved.