菜单
Use after circuit-design produces a validated BOM (specs/bom.md) to plan exact component placement coordinates and wiring before schematic capture begins. Pure planning — no file modifications.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
| name | schematic-plan |
| description | Use after circuit-design produces a validated BOM (specs/bom.md) to plan exact component placement coordinates and wiring before schematic capture begins. Pure planning — no file modifications. |
EVERY KiCad operation has a corresponding MCP tool. Do NOT claim a tool does not exist without first listing all available tools. Key tools that MUST be used instead of file writes:
add_symbol — create custom symbol definitions in .kicad_sym filescreate_symbol_library — create new .kicad_sym library filescreate_schematic — create new .kicad_sch filescreate_project — create new .kicad_pro project files
If you find yourself thinking "there's no MCP tool for this," you are
wrong. Check the tool list again.
Pure planning phase — no file modifications. Only inspection MCP
tools (list_lib_symbols, get_symbol_info). Note:
get_symbol_pins requires a schematic with placed symbols and cannot
be used during planning. Use get_symbol_info instead — it reads
pin definitions directly from library files.
Inputs: specs/bom.md (validated BOM from circuit-design)
Outputs: specs/schematic-plan.md (placement and wiring plan)
When this skill activates, print exactly:
Using schematic-plan to plan placement and wiring from the validated BOM.
Then immediately proceed to the Pre-flight checks. This is a
mechanical planning phase — do not ask the user what to do. Read
specs/bom.md and execute the planning steps.
Report progress at natural milestones (after page size calculation, after coordinate assignment, after wiring plan). Keep status updates to one line each.
specs/bom.md existsvalidate_hierarchy to inspect current annotation state —
the plan must account for existing ref conflictsCount components per stage. Estimate space using spacing rules:
Calculate total bounding box. Pick smallest standard page that fits. Record decision and math explicitly (show the arithmetic).
Standard page sizes (landscape):
| Size | Width (mm) | Height (mm) | Usable W | Usable H |
|---|---|---|---|---|
| A4 | 297 | 210 | 179 | 168 |
| A3 | 420 | 297 | 302 | 255 |
| A2 | 594 | 420 | 476 | 378 |
Usable W = width - 20 (margins) - 108 (title block width near bottom-right). Usable H = height - 20 (margins) - 32 (title block height).
Assign each functional stage a bounding box on the sheet:
## Stage Layout
| Stage | Bounding Box | Components |
|-------|-------------|------------|
| Input protection | (25, 50) -> (140, 90) | J1, F1, D1, C1, C2, Q1, D3, R5 |
| Buck converter | (25, 115) -> (240, 170) | U1, C3, C4, ... |
Assign exact (x, y) per component within its stage bounding box:
## Placement
| Ref | lib_id | x | y | rotation | Stage |
|-----|--------|---|---|----------|-------|
| J1 | Connector_Generic:Conn_01x02 | 25.4 | 50.8 | 0 | Input protection |
For each net, specify tool and connections. Available tools:
connect_pins — direct Manhattan wire between two adjacent pinswire_pins_to_net — connect one or more pins to a named net labelGroup all pins for the same net into a single wire_pins_to_net
call. Do not make separate calls for individual pins on the same net.
Wiring order follows table order top-to-bottom; list power nets
before signal nets.
## Wiring
| Order | Net | Tool | Pins |
|-------|-----|------|------|
| 1 | J1:1 -> F1:1 | connect_pins | Direct, adjacent |
| 2 | VIN | wire_pins_to_net | F1:2, D1:K, C1:1, C2:1, Q1:S, D3:K |
| 3 | PGND | wire_pins_to_net | J1:2, D1:A, C1:2, C2:2, R5:2 |
List pins needing no-connect flags and nets needing PWR_FLAG.
## No-Connect Pins
| Ref | Pin | Reason |
|-----|-----|--------|
| U1 | NC | Unused pin per datasheet |
## Power Flags
| Net | Reason |
|-----|--------|
| VOUT | Regulator output, not recognized as power source by KiCad |
If the design requires multiple sheets, plan sheet boundaries and hierarchical labels here.
These are the ONLY kicad MCP tools you should use during planning (inspection only — no modifications):
Symbol and footprint lookup:
list_lib_symbols — verify symbol exists in libraryget_symbol_info — get pin names, types, and propertieslist_lib_footprints — verify footprint existsget_footprint_info — check pad dimensionsSchematic inspection (if schematic already exists):
get_schematic_summary — get item counts for a sheetlist_schematic_components — list symbols on a sheetlist_schematic_labels — list net labels on a sheetlist_schematic_wires — list wires on a sheetlist_schematic_global_labels — list global labels on a sheetlist_schematic_hierarchical_labels — list hierarchical labels on a sheetlist_schematic_sheets — list hierarchical sheet blocks on a sheetlist_schematic_junctions — list junctions on a sheetlist_schematic_no_connects — list no-connect flags on a sheetlist_schematic_bus_entries — list bus entries on a sheetis_root_schematic — check if a schematic is root or sub-sheetlist_hierarchy — view the full sheet hierarchy treeget_sheet_info — get sheet details with pin/label matching statusvalidate_hierarchy — check for orphaned labels/pins, direction mismatches, duplicate refs
Run validate_hierarchy before planning to understand existing
annotation state. If it reports duplicate_ref or unannotated_ref,
the plan should include an annotation step.list_cross_sheet_nets — list all nets crossing sheet boundariesget_symbol_instances — list symbol instances from root schematictrace_hierarchical_net — trace a net across the hierarchy to understand
existing cross-sheet connections before planning new onesDo NOT use get_symbol_pins — it requires a placed schematic.
Use get_symbol_info instead.
After writing specs/schematic-plan.md, dispatch the schematic plan
reviewer subagent:
Agent(
prompt="<contents of agents/schematic-plan-reviewer.md>\n\nPlan path: <project_dir>/specs/schematic-plan.md\nBOM path: <project_dir>/specs/bom.md",
subagent_type="general-purpose"
)
Fix any issues reported by the reviewer, update
specs/schematic-plan.md, and re-dispatch until the reviewer returns
APPROVED.
User rejection handling: If the user rejects the plan or requests changes (e.g., different stage layout, different page size), fix the specific issues and re-run the schematic plan reviewer.
IMPORTANT: Use TodoWrite to create todos for EACH checklist item below.
specs/bom.md exists and is APPROVEDspecs/schematic-plan.md artifact| Thought | Reality |
|---|---|
| "A4 is big enough" | Show the math. Components * spacing + margins + title block. |
| "These coordinates look right" | Check every Y < page_height - margin, every X < page_width - margin. |
| "I know this pin name" | Call get_symbol_info. Don't guess pin names from memory. |
| "The spacing is fine" | Minimum 10.16mm vertical, 12.7mm horizontal. Measure, don't eyeball. |
mkdir -p skills/schematic-plangit commit -m "feat: add schematic-plan skill for placement and wiring planning" (NO Co-Authored-By)Use when placing footprints on a PCB, routing traces, adding vias or copper zones, deciding trace widths, or planning board layout strategy. Also use when the user asks about PCB stackup, ground planes, trace spacing, or component placement on a board.
Use when executing a schematic placement plan (plan mode) or modifying an existing schematic (modification mode).
Use when starting any conversation involving electronics, KiCad, PCB design, schematic capture, circuit design, or EDA tasks.
Use when running ERC or DRC checks, fixing electrical or design rule violations, debugging unconnected nets, resolving "power pin not driven" errors, or preparing a design for manufacturing export. Also use when the user says "my ERC has errors" or "DRC is failing."
Use when designing an electronic circuit from requirements, choosing topology or regulator type, selecting component values, planning protection circuits, or deciding what goes on a board before schematic capture begins. Also use when the user asks "what components do I need" or "how should I power this."