菜单
Compile a named Chisel module to Verilog using sbt, outputting to the module's workspace directory.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Run full Chipyard-to-ORFS PnR flow for large designs (SmallBOOM etc.) using All-Mock memory blackboxing in Docker: generate RTL, preprocess nosram, run multi-round ORFS synth->finish with mock SRAMs to avoid OOM.
Docker Chipyard flow: generate RTL from a Chipyard config via Docker, run SRAM mapping, stage artifacts into MyDesign, and hand off to PnR.
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration in Docker: generate RTL from Chipyard Docker, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal PPA.
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration: generate RTL from Chipyard with ENABLE_YOSYS_FLOW, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal PPA.
Unified Chipyard PnR flow: automatically routes to local or Docker workflow based on backend_mode setting.
Unified Chipyard flow: automatically routes to local or Docker workflow based on backend_mode setting.
| name | compile |
| description | Compile a named Chisel module to Verilog using sbt, outputting to the module's workspace directory. |
| disable-model-invocation | true |
| allowed-tools | ["Bash","Read"] |
Compile a Chisel module to Verilog, placing output in the module's workspace directory.
/chip-agent:compile <ModuleName>
Extract module name from $ARGUMENTS. If empty or blank, ask the user: "Which module should I compile? Please provide a PascalCase module name (e.g., ALU, Counter, TrivialModule)."
Validate module name. The name must be PascalCase: first character uppercase, no spaces, no hyphens, only alphanumeric characters. If invalid, inform the user and ask for a corrected name.
Determine the project root directory by finding the nearest ancestor directory of this skill file that contains .claude. Use that directory as the base for all paths below.
Run compilation. Execute the compile script with the workspace path:
<project-root>/scripts/compile.sh workspace/<ModuleName>
On success: List the generated files in workspace/<ModuleName>/generated/ so the user can see what was produced. Mention that they can now run /chip-agent:lint <ModuleName> to check the output.
On failure: Show the build error output. Suggest checking the Chisel source at chisel-project/src/main/scala/chipagent/<ModuleName>.scala for issues.
$ARGUMENTS -- A PascalCase module name (e.g., ALU, Counter, TrivialModule).
Generated Verilog files in workspace/<ModuleName>/generated/ (.v and .sv files).