compile

Compile a named Chisel module to Verilog using sbt, outputting to the module's workspace directory.

安装方式

默认使用会先检查来源的 Prompt；你也可以切换为直接命令，或下载本地副本。

用 Codex 或 Claude 帮你安装复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。

直接命令不会经过审查 Prompt；运行前请先检查来源。

npx skills add https://github.com/xsw632/ChipAgent --skill compile

命令会保持在同一行。复制前请横向滚动并检查完整内容。

想先保存到本地？可下载 SkillsMP 当前能够提供的文件。

决定是否安装前，请先阅读 SKILL.md，以及 SkillsMP 当前展示的配套文件。

SKILL.md

来源说明 · 只读预览

name	compile
description	Compile a named Chisel module to Verilog using sbt, outputting to the module's workspace directory.
disable-model-invocation	true
allowed-tools	["Bash","Read"]

Compile a Chisel module to Verilog, placing output in the module's workspace directory.

/chip-agent:compile <ModuleName>

Extract module name from $ARGUMENTS. If empty or blank, ask the user: "Which module should I compile? Please provide a PascalCase module name (e.g., ALU, Counter, TrivialModule)."
Validate module name. The name must be PascalCase: first character uppercase, no spaces, no hyphens, only alphanumeric characters. If invalid, inform the user and ask for a corrected name.
Determine the project root directory by finding the nearest ancestor directory of this skill file that contains .claude. Use that directory as the base for all paths below.
Run compilation. Execute the compile script with the workspace path:
```
<project-root>/scripts/compile.sh workspace/<ModuleName>
```
On success: List the generated files in workspace/<ModuleName>/generated/ so the user can see what was produced. Mention that they can now run /chip-agent:lint <ModuleName> to check the output.
On failure: Show the build error output. Suggest checking the Chisel source at chisel-project/src/main/scala/chipagent/<ModuleName>.scala for issues.

$ARGUMENTS -- A PascalCase module name (e.g., ALU, Counter, TrivialModule).

Generated Verilog files in workspace/<ModuleName>/generated/ (.v and .sv files).