xsw632
xsw632/ChipAgent
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
直接命令不会经过审查 Prompt；运行前请先检查来源。
npx skills add https://github.com/xsw632/ChipAgent --skill lint命令会保持在同一行。复制前请横向滚动并检查完整内容。
想先保存到本地？可下载 SkillsMP 当前能够提供的文件。
Run full Chipyard-to-ORFS PnR flow for large designs (SmallBOOM etc.) using All-Mock memory blackboxing in Docker: generate RTL, preprocess nosram, run multi-round ORFS synth->finish with mock SRAMs to avoid OOM.
Docker Chipyard flow: generate RTL from a Chipyard config via Docker, run SRAM mapping, stage artifacts into MyDesign, and hand off to PnR.
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration in Docker: generate RTL from Chipyard Docker, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal PPA.
基于 SOC 职业分类
正在显示 SKILL.md
| name | lint |
| description | Run Verilator lint checks on generated Verilog for a named module in its workspace directory. |
| disable-model-invocation | true |
| allowed-tools | ["Bash","Read"] |
Run Verilator lint-only checks on the generated Verilog for a named module.
/chip-agent:lint <ModuleName>
Extract module name from $ARGUMENTS. If empty or blank, ask the user: "Which module should I lint? Please provide a PascalCase module name (e.g., ALU, Counter, TrivialModule)."
Check prerequisites. Verify that workspace/<ModuleName>/generated/ exists and contains at least one .v file. If not, tell the user: "No generated Verilog found. Please run /chip-agent:compile <ModuleName> first."
Determine the project root directory by finding the nearest ancestor directory of this skill file that contains .claude. Use that directory as the base for all paths below.
Run lint. Execute the lint script with the workspace path:
<project-root>/scripts/lint.sh workspace/<ModuleName>
On success (exit 0): Report that lint passed. Check if workspace/<ModuleName>/generated/lint-warnings.log exists and is non-empty. If so, list the suppressed warnings. Mention that the user can now run /chip-agent:simulate <ModuleName>.
On failure (non-zero exit): Show the Verilator lint errors. Suggest fixing the Chisel source at chisel-project/src/main/scala/chipagent/<ModuleName>.scala -- do not edit the generated Verilog directly.
$ARGUMENTS -- A PascalCase module name (e.g., ALU, Counter, TrivialModule).
Lint pass/fail report. If warnings were suppressed, they are listed from workspace/<ModuleName>/generated/lint-warnings.log.