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block-requirements-normalizer

Normalize a block-level design brief into deterministic requirements, explicit PPA targets, and open intake questions. Use this skill whenever the user provides high-level microarchitectural intent and the workflow must capture power, performance, and area before specification or RTL work begins.

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安装命令

npx skills add https://github.com/asicdesign-ai/asic-ai-workflows --skill block-requirements-normalizer

复制此命令并粘贴到 Claude Code 中以安装该技能

来源

asicdesign-ai/asic-ai-workflows

星标3

分支2

更新时间2026年4月8日 06:34

SKILL.md

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name	block-requirements-normalizer
description	Normalize a block-level design brief into deterministic requirements, explicit PPA targets, and open intake questions. Use this skill whenever the user provides high-level microarchitectural intent and the workflow must capture power, performance, and area before specification or RTL work begins.

Block Requirements Normalizer Skill

Convert a user brief into one structured requirement set for a block-level RTL planning flow.

Scope: block or small IP. This is an intake and normalization skill, not a microarchitecture or RTL generator.

Rules

Apply these repo rules before analysis and output generation:

../../rules/common/evidence-grounding.md
../../rules/common/output-discipline.md
../../rules/arch/requirements-traceability.md
../../rules/arch/ppa-capture.md

Analysis

Read the user brief and any optional RTL context, then perform these steps:

Extract atomic block requirements and assign stable REQ-NNN IDs.
Separate functional, interface, clock/reset, and PPA requirements.
Capture performance, power, and area independently as numeric, qualitative, or missing.
Emit blocking open questions whenever the intake does not support specification work, especially for missing PPA.
Keep descriptions short, factual, and grounded in the provided brief.

Output Format

Produce a single YAML document:

design:
  top_module: event_counter
  brief_summary: "Programmable event counter with optional interrupt threshold."

requirements:
  - id: REQ-001
    title: count qualified input events
    category: function
    priority: must
    source: user
    description: "The block increments a stored count when event_valid is asserted."
    acceptance_criteria: "With counting enabled, each qualified event increments count_value by one."

ppa_targets:
  performance:
    target: "600"
    units: "MHz"
    priority: "primary"
    status: numeric
  power:
    target: "minimize dynamic power"
    units: null
    priority: "secondary"
    status: qualitative
  area:
    target: null
    units: null
    priority: "secondary"
    status: missing

open_questions:
  - topic: area target
    question: "What area budget or utilization limit constrains the block?"
    blocking: true
    related_requirement_ids:
      - REQ-001

summary:
  total_requirements: 1
  total_open_questions: 1
  ppa_complete: false

Scope Limitations

Can do: normalize intent, capture explicit PPA status, and surface missing intake data.
Cannot do: derive a complete microarchitecture, choose undocumented protocols, or claim front-end closure.

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asicdesign-ai/asic-ai-workflows

Extract a source-grounded, AI-readable textual design view from HDL source, parser output, MCP tool output, or model reasoning. Use this skill when the user needs Verilog, SystemVerilog, VHDL, or proprietary hardware description language normalized into a reusable design view for downstream analysis flows such as timing, lint, CDC, RDC, formal planning, or DV planning. Prefer UHDM text for SystemVerilog/Verilog when available, AST JSON when UHDM is not available, and explicit model-derived views only when no tool evidence exists.

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rtl-timing-analyzer

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Analyze an HDL design view or visible RTL for pre-synthesis timing risk by estimating combinational logic depth on register-to-register and boundary timing paths. Use this skill when the user already has a UHDM text dump, AST JSON, source-grounded textual design view, or small visible RTL block and asks for critical paths, deep combinational logic, reg-to-reg timing risk, or pre-synthesis timing feedback. This skill is analysis-only; use an HDL-design-view extraction skill or flow when parser/tool/MCP selection, source-language normalization, or design-view generation is required.

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rtl-designer

asicdesign-ai/asic-ai-workflows

Read an approved microarchitecture specification and emit synthesizable SystemVerilog with requirement traceability. Use this skill whenever the flow moves from block architecture into concrete RTL implementation.

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rtl-lint-auditor

asicdesign-ai/asic-ai-workflows

Review synthesizable SystemVerilog for static RTL issues such as inferred latches, reset mismatches, width hazards, and multi-driver structure. Use this skill whenever generated RTL needs a deterministic front-end lint audit before CDC, RDC, or timing review.

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block-rtl-package-assembler

asicdesign-ai/asic-ai-workflows

Assemble normalized requirements, the microarchitecture spec, generated RTL, and static audit summaries into one front-end handoff package. Use this skill whenever the block-level RTL planning flow needs one deterministic output that can feed downstream DV planning.

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microarchitecture-spec-author

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Turn normalized block requirements into a Markdown microarchitecture specification with requirement traceability and targeted diagrams. Use this skill whenever the workflow needs a deterministic architecture document before RTL generation.

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来源

asicdesign-ai

asicdesign-ai/asic-ai-workflows

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安装命令

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在 Manus 中运行

适用职业SOC

电子工程师（非计算机）建筑与工程类职业17-2072L4

name	block-requirements-normalizer
description	Normalize a block-level design brief into deterministic requirements, explicit PPA targets, and open intake questions. Use this skill whenever the user provides high-level microarchitectural intent and the workflow must capture power, performance, and area before specification or RTL work begins.

Block Requirements Normalizer Skill

Convert a user brief into one structured requirement set for a block-level RTL planning flow.

Scope: block or small IP. This is an intake and normalization skill, not a microarchitecture or RTL generator.

Rules

Apply these repo rules before analysis and output generation:

../../rules/common/evidence-grounding.md
../../rules/common/output-discipline.md
../../rules/arch/requirements-traceability.md
../../rules/arch/ppa-capture.md

Analysis

Read the user brief and any optional RTL context, then perform these steps:

Extract atomic block requirements and assign stable REQ-NNN IDs.
Separate functional, interface, clock/reset, and PPA requirements.
Capture performance, power, and area independently as numeric, qualitative, or missing.
Emit blocking open questions whenever the intake does not support specification work, especially for missing PPA.
Keep descriptions short, factual, and grounded in the provided brief.

Output Format

Produce a single YAML document:

design:
  top_module: event_counter
  brief_summary: "Programmable event counter with optional interrupt threshold."

requirements:
  - id: REQ-001
    title: count qualified input events
    category: function
    priority: must
    source: user
    description: "The block increments a stored count when event_valid is asserted."
    acceptance_criteria: "With counting enabled, each qualified event increments count_value by one."

ppa_targets:
  performance:
    target: "600"
    units: "MHz"
    priority: "primary"
    status: numeric
  power:
    target: "minimize dynamic power"
    units: null
    priority: "secondary"
    status: qualitative
  area:
    target: null
    units: null
    priority: "secondary"
    status: missing

open_questions:
  - topic: area target
    question: "What area budget or utilization limit constrains the block?"
    blocking: true
    related_requirement_ids:
      - REQ-001

summary:
  total_requirements: 1
  total_open_questions: 1
  ppa_complete: false

Scope Limitations

Can do: normalize intent, capture explicit PPA status, and surface missing intake data.
Cannot do: derive a complete microarchitecture, choose undocumented protocols, or claim front-end closure.