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ball

Create a new Buckyball Ball operator named $ARGUMENTS, covering the full flow from implementation to verification.

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概览

Create a new Buckyball Ball operator named $ARGUMENTS, covering the full flow from implementation to verification.

安装命令

npx skills add https://github.com/DangoSys/buckyball --skill ball

复制此命令并粘贴到 Claude Code 中以安装该技能

来源

DangoSys/buckyball

星标60

分支29

更新时间2026年5月24日 16:25

SKILL.md

readonly

name	ball
description	Create a new Buckyball Ball operator named $ARGUMENTS, covering the full flow from implementation to verification.

Important: all build/simulation operations must go through MCP tools (validate, bbdev_workload_build, bbdev_verilator_run, etc.). Do not use bbdev CLI or nix develop directly.

Phase 1 - Requirement Collection

Inspect registration state and decide ballId + funct7:
- arch/src/main/scala/framework/balldomain/configs/default.json
- arch/src/main/scala/examples/toy/balldomain/DISA.scala
Check for partial existing implementation (incremental mode):
- existing directory in arch/src/main/scala/framework/balldomain/prototype/
- existing ISA macro in bb-tests/workloads/lib/bbhw/isa/
- existing CTest in bb-tests/workloads/src/CTest/toy/
Confirm with user:
- operator semantics
- inBW / outBW
- whether op2 is needed
- meaning of iter

Phase 2 - Implement the Ball

Read references:
- simple example: .../prototype/relu/ReluBall.scala, Relu.scala
- complex example: .../prototype/systolicarray/
- Blink protocol: .../blink/blink.scala, bank.scala, status.scala
- SRAM IO: .../memdomain/backend/banks/SramIO.scala
Create files under arch/src/main/scala/framework/balldomain/prototype/<name>/ using templates from references/.

Key constraints

SRAM read latency is 1 cycle (resp.valid in the cycle after req.fire)
Latch command fields when cmdReq.fire
Base FSM pattern: idle -> read -> compute -> write -> complete -> idle
status.idle and status.running must map correctly to FSM states

Phase 3 - Register the Ball

Update files in order:

.../configs/default.json - append ballIdMappings entry and update ballNum
.../bbus/busRegister.scala - add import + match case
.../DISA.scala - add val XXX = BitPat("bxxxxxxx")
.../DomainDecoder.scala - add decode row (BID = ballId.U)

Phase 4 - Add ISA C Macro

Create <funct7_decimal>_<name>.c under bb-tests/workloads/lib/bbhw/isa/, then include it in isa.h.

Phase 5 - Add CTest

Create <name>_test.c under bb-tests/workloads/src/CTest/toy/
Register in bb-tests/workloads/src/CTest/toy/CMakeLists.txt using add_cross_platform_test_target

Phase 6 - Validate, Build, and Simulate

Run validate and ensure all 6 invariants pass
Run bbdev_workload_build
Run bbdev_verilator_run for this Ball's CTest binary
Interpret results:
- PASSED -> done
- FAILED -> switch to /debug

同仓库更多 Skills

同仓库

verify

DangoSys/buckyball

Verify functional correctness of the Ball named $ARGUMENTS. Use this skill when users ask to verify/test a Ball, check whether a Ball works correctly, or validate a newly created Ball.

2026-05-2460

check

DangoSys/buckyball

Staticaly validate Buckyball Ball registration consistency and optionally auto-fix mismatches. Use this skill when users ask to inspect registration status, validate Ball configuration, troubleshoot registration issues, or verify consistency after registration edits.

2026-04-0860

debug

DangoSys/buckyball

Systematically debug Buckyball simulation failures. Use this skill when simulation returns FAILED, CTest fails, Chisel compilation errors appear, or users report abnormal Ball behavior. It covers log analysis, waveform analysis, and common failure pattern matching.

2026-04-0860

optimize

DangoSys/buckyball

Analyze and optimize latency and area for the RTL module named $ARGUMENTS. Applies to any RTL module (Ball, MemFrontend, BBus, GlobalROB, etc.), not limited to Ball operators.

2026-04-0860

waveform

DangoSys/buckyball

Use waveform-mcp tools to analyze VCD/FST waveforms and inspect Buckyball signal timing. Use this skill for cycle-level timing analysis, handshake debugging, FSM transition checks, or whenever waveform-level evidence is needed.

2026-04-0860

来源

DangoSys

DangoSys/buckyball

打开 GitHub 仓库查看创作者相关仓库

安装命令

下载

在 Manus 中运行

适用职业SOC

软件开发工程师计算机与数学类职业15-1252L4

name	ball
description	Create a new Buckyball Ball operator named $ARGUMENTS, covering the full flow from implementation to verification.

Important: all build/simulation operations must go through MCP tools (validate, bbdev_workload_build, bbdev_verilator_run, etc.). Do not use bbdev CLI or nix develop directly.

Phase 1 - Requirement Collection

Inspect registration state and decide ballId + funct7:
- arch/src/main/scala/framework/balldomain/configs/default.json
- arch/src/main/scala/examples/toy/balldomain/DISA.scala
Check for partial existing implementation (incremental mode):
- existing directory in arch/src/main/scala/framework/balldomain/prototype/
- existing ISA macro in bb-tests/workloads/lib/bbhw/isa/
- existing CTest in bb-tests/workloads/src/CTest/toy/
Confirm with user:
- operator semantics
- inBW / outBW
- whether op2 is needed
- meaning of iter

Phase 2 - Implement the Ball

Read references:
- simple example: .../prototype/relu/ReluBall.scala, Relu.scala
- complex example: .../prototype/systolicarray/
- Blink protocol: .../blink/blink.scala, bank.scala, status.scala
- SRAM IO: .../memdomain/backend/banks/SramIO.scala
Create files under arch/src/main/scala/framework/balldomain/prototype/<name>/ using templates from references/.

Key constraints

SRAM read latency is 1 cycle (resp.valid in the cycle after req.fire)
Latch command fields when cmdReq.fire
Base FSM pattern: idle -> read -> compute -> write -> complete -> idle
status.idle and status.running must map correctly to FSM states

Phase 3 - Register the Ball

Update files in order:

.../configs/default.json - append ballIdMappings entry and update ballNum
.../bbus/busRegister.scala - add import + match case
.../DISA.scala - add val XXX = BitPat("bxxxxxxx")
.../DomainDecoder.scala - add decode row (BID = ballId.U)

Phase 4 - Add ISA C Macro

Create <funct7_decimal>_<name>.c under bb-tests/workloads/lib/bbhw/isa/, then include it in isa.h.

Phase 5 - Add CTest

Create <name>_test.c under bb-tests/workloads/src/CTest/toy/
Register in bb-tests/workloads/src/CTest/toy/CMakeLists.txt using add_cross_platform_test_target

Phase 6 - Validate, Build, and Simulate

Run validate and ensure all 6 invariants pass
Run bbdev_workload_build
Run bbdev_verilator_run for this Ball's CTest binary
Interpret results:
- PASSED -> done
- FAILED -> switch to /debug