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ecp5-sv-yosys-verilator

Use this skill whenever writing, reviewing, or debugging SystemVerilog for Lattice ECP5 FPGAs that must be compatible with both Yosys (nextpnr synthesis) and Verilator (simulation). Covers ECP5-specific primitives (EHXPLLL, DP16KD, PDPW16KD, MULT18X18D, ALU54B, DCCA, ODDRX1F, OSCG, JTAGG, USRMCLK, GSR, etc.), correct explicit instantiation patterns, Verilator stub strategies, macro guards, resource budgeting for ECP5-25K, and common pitfalls. Trigger on any mention of ECP5, nextpnr, Yosys synthesis with Verilator cosim, FPGA primitives in SV, DSP multipliers, block RAM configurations, or questions about making vendor hard IP simulate correctly. Use when the user asks about block RAM aspect ratios, DSP pipeline registers, dual/single-port RAM configs, or wants to explicitly instantiate limited hard resources rather than relying on inference.

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概览

Use this skill whenever writing, reviewing, or debugging SystemVerilog for Lattice ECP5 FPGAs that must be compatible with both Yosys (nextpnr synthesis) and Verilator (simulation). Covers ECP5-specific primitives (EHXPLLL, DP16KD, PDPW16KD, MULT18X18D, ALU54B, DCCA, ODDRX1F, OSCG, JTAGG, USRMCLK, GSR, etc.), correct explicit instantiation patterns, Verilator stub strategies, macro guards, resource budgeting for ECP5-25K, and common pitfalls. Trigger on any mention of ECP5, nextpnr, Yosys synthesis with Verilator cosim, FPGA primitives in SV, DSP multipliers, block RAM configurations, or questions about making vendor hard IP simulate correctly. Use when the user asks about block RAM aspect ratios, DSP pipeline registers, dual/single-port RAM configs, or wants to explicitly instantiate limited hard resources rather than relying on inference.

安装命令
npx skills add https://github.com/londey/ecp5-sv-yosys-verilator-skill --skill ecp5-sv-yosys-verilator

复制此命令并粘贴到 Claude Code 中以安装该技能

来源
londey/ecp5-sv-yosys-verilator-skill
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更新时间2026年3月28日 03:17
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