chipweaver/veripower

lint-cdc

Use when running SpyGlass lint or CDC checks, analyzing violations, adding waivers, supplementing SGDC annotations, or re-running after RTL changes; not for synthesis or simulation.

لغة النص الأصلي: الإنجليزية

power-analysis

Use when running gate-level power simulation + PT-PX averaged power analysis (SAIF flow) for PPA gating; not for RTL functional simulation, static timing, or time-resolved waveforms.

لغة النص الأصلي: الإنجليزية

rtl-design

Use when writing or modifying Verilog/SystemVerilog RTL, or recording each child's file layout and constraint annotations; not for verification, lint, or synthesis.

لغة النص الأصلي: الإنجليزية

simulation-plan

Use when generating or evolving the verification plan, scaffold specification, testpoints, and power scenarios for a module; not for materializing UVM TB or running EDA tools.

لغة النص الأصلي: الإنجليزية

simulation

Use when materializing and running a module's UVM TB from an approved verification plan (regression, coverage); not for plan authoring or RTL changes.

لغة النص الأصلي: الإنجليزية

simulation-triage

Use when a simulation run fails and root-cause analysis is needed before a rework decision; not for fixing code, modifying state, or running regression.

لغة النص الأصلي: الإنجليزية

specification

Use when writing or reviewing design specification (design.md), defining interfaces or constraints (SDC/SGDC), or updating from rework feedback; not for RTL implementation or verification.

لغة النص الأصلي: الإنجليزية

synthesis

Use when running Design Compiler synthesis, analyzing timing/area/power reports, supplementing SDC exceptions, or re-synthesizing after RTL changes; not for power analysis or static timing.

لغة النص الأصلي: الإنجليزية

timing-analysis

Use when running static timing analysis on synthesis netlist, analyzing setup/hold violations, reviewing timing reports, or re-analyzing after synthesis changes; not for synthesis or power analysis.

لغة النص الأصلي: الإنجليزية

brainstorm

Use when brainstorming a new module's requirements and architecture to produce the brainstorm.md the pipeline starts from; not for design.md, RTL, constraints, or any in-pipeline stage.

لغة النص الأصلي: الإنجليزية

design-flow

Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.

لغة النص الأصلي: الإنجليزية

env-precheck

Use when checking whether this machine's Python, EDA tools and licenses can actually run VeriPower's stages; not for any pipeline stage, module state, or design work.

لغة النص الأصلي: الإنجليزية