systemverilog-rtl-design

name	SystemVerilog RTL Design
description	Provides RTL design patterns, synthesis guidelines, and coding templates. Use when the user mentions 'module design', 'FSM', 'state machine', 'pipeline', 'synthesizable', 'parameterize', 'parameter', 'localparam', 'clock domain', 'CDC', 'FIFO', 'register file', 'always_ff', 'always_comb', 'generate', or asks about synthesis-related coding.
version	1.0.0

SystemVerilog RTL Design Reference

Coding Standards

Signal Declarations

// Preferred: logic for all signals
logic [7:0] data;
logic       valid;

// Avoid: reg/wire (older style)
// reg [7:0] data;   // Don't use
// wire valid;        // Don't use

Always Blocks

Block Type	Use Case	Assignment
always_ff	Sequential logic (flip-flops)	Non-blocking <=
always_comb	Combinational logic	Blocking =
always_latch	Latches (avoid!)	Blocking =

// Sequential - non-blocking
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        q <= '0;
    else
        q <= d;
end

// Combinational - blocking
always_comb begin
    y = a & b;
    z = y | c;  // Uses updated y
end

Design Patterns

Parameterized Module

module fifo #(
    parameter int WIDTH = 8,
    parameter int DEPTH = 16,
    parameter bit FWFT  = 1'b0  // First-word-fall-through
) (
    input  logic             clk,
    input  logic             rst_n,
    // Write interface
    input  logic [WIDTH-1:0] wr_data,
    input  logic             wr_en,
    output logic             full,
    // Read interface
    output logic [WIDTH-1:0] rd_data,
    input  logic             rd_en,
    output logic             empty
);
    localparam int ADDR_WIDTH = $clog2(DEPTH);

    // Memory array
    logic [WIDTH-1:0] mem [DEPTH];

    // Pointers
    logic [ADDR_WIDTH:0] wr_ptr, rd_ptr;  // Extra bit for full/empty

    // ... implementation
endmodule