القائمة
جمع SkillsMP عدد ١٧ من skills من hdl-tools/analog-chip-design-agents. افتح أي skill لمراجعة مصدره وتفاصيله.
عرض ١٧ من أصل ١٧ skills مجمعة.
Distil append-only experiences.jsonl run records into per-domain knowledge.md summaries for the analog design agents. Use after enough runs accumulate to merge new convergence fixes, sizing recipes, PDK quirks, and tool flags into the Tier-2 knowledge file.
لغة النص الأصلي: الإنجليزية
Analog circuit (schematic) design — topology selection, device sizing via gm/Id, biasing, schematic capture, pre-layout ERC, and design review. Use when designing an op-amp, comparator, bandgap, LDO, bias generator, or any analog block from a block…
لغة النص الأصلي: الإنجليزية
EDA tool detection, wrapper deployment, and MCP configuration for analog/mixed-signal + RF design environments. Use when setting up a workstation, verifying tool availability before a domain flow, or generating per-tool install scripts with TCL modulefiles.
لغة النص الأصلي: الإنجليزية
Floorplan, generate matched devices, and place/route analog blocks with symmetry, shielding, and matching constraints to a clean, DRC-ready layout. Use when turning a sign-off-ready schematic into a GDS layout, or servicing a fix_request that repairs the…
لغة النص الأصلي: الإنجليزية
Run DRC, LVS, antenna/ERC, and density/DFM checks on an analog layout and sign off a physically-clean GDS. Use when verifying a custom layout against the foundry rule deck and the source netlist, or re-validating after a custom-layout fix_request was…
لغة النص الأصلي: الإنجليزية
Cross-domain loop orchestration for the analog/mixed-signal + RF design pipeline. Provides the fix_request protocol, iteration-cap logic, the authoritative design_state.json constraints schema, failure classification, and approval checkpoints. Use when…
لغة النص الأصلي: الإنجليزية
Solve the electromagnetics of an on-chip passive or antenna (inductor, transformer, transmission line, balun, antenna), extract a converged passive S-parameter model, and fit a lumped equivalent for circuit-level RF simulation. Use when building the passive…
لغة النص الأصلي: الإنجليزية
Design and verify an RF/mmWave block (LNA, mixer, VCO, PLL, PA): topology selection and matching, S-parameter, harmonic-balance, Pnoise/PAC, IP3, and load-pull analyses, signed off against the RF spec table across corners. Use when designing or re-running an…
لغة النص الأصلي: الإنجليزية
Qualify analog IP, assemble the mixed-signal top, define boundary/connect rules, run chip-level AMS simulation, and check power intent through integration sign-off. Use when integrating signed-off analog/RF blocks into a mixed-signal top, or re-validating…
لغة النص الأصلي: الإنجليزية
Run electromigration, IR-drop, ESD, latch-up, and aging (HCI/NBTI) analyses on a signed-off analog layout and sign off long-term reliability. Use when verifying that power/signal routing and devices survive the rated current, voltage, and lifetime, or…
لغة النص الأصلي: الإنجليزية
Characterize timing, power, and noise of a signed-off analog/mixed macro across PVT corners and generate validated Liberty (.lib) + behavioral models for downstream integration. Use when building the abstract views a chip-level / digital flow consumes, or…
لغة النص الأصلي: الإنجليزية
Run RC and coupling extraction on the verified layout and build a back-annotated post-layout netlist for sign-off simulation. Use when extracting parasitics from a physically-clean GDS, building the PEX netlist for post-layout sign-off, or flagging a layout…
لغة النص الأصلي: الإنجليزية
Run post-PEX corner and Monte-Carlo simulation on the extracted netlist, re-verify specs against the pre-layout design, and gate tape-out. Use when closing a block's specs on the extracted netlist, quantifying parasitic degradation, or driving the tape-out…
لغة النص الأصلي: الإنجليزية
Build mixed-signal testbenches, define connect rules, run analog-digital co-simulation and real-number-model regressions, and close functional coverage. Use when verifying an analog/mixed-signal block against its digital control across corners, or…
لغة النص الأصلي: الإنجليزية
Capture top-level analog/mixed-signal specs, budget noise/linearity/power across a signal chain, allocate per-block specifications, and assess feasibility before circuit design begins. Use when planning a receiver front-end, data-converter front-end, sensor…
لغة النص الأصلي: الإنجليزية
Author, compile, and validate analog behavioral models — Verilog-A, Verilog-AMS, VHDL-AMS, and SystemVerilog real-number models — plus the connect modules that bridge analog and digital domains. This is the analog-HDL core of the marketplace. Use when…
لغة النص الأصلي: الإنجليزية
Analog circuit simulation — testbench setup, DC operating point, AC, transient, noise, stability, PVT corners, and Monte-Carlo yield analysis, ending in electrical-spec sign-off. Use when verifying an analog block's specs across corners, debugging…
لغة النص الأصلي: الإنجليزية