القائمة
PCB layout and routing. Component placement, trace routing, copper pours, design rule configuration, and layout optimization for manufacturability.
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npx skills add https://github.com/l3wi/claude-eda --skill eda-pcbيبقى الأمر في سطر واحد. مرّر أفقيًا لمراجعته كاملًا قبل النسخ.
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عرض SKILL.md
| name | eda-pcb |
| description | PCB layout and routing. Component placement, trace routing, copper pours, design rule configuration, and layout optimization for manufacturability. |
| allowed-tools | Read, Write, Glob, mcp__kicad-pcb__create_project, mcp__kicad-pcb__open_project, mcp__kicad-pcb__save_project, mcp__kicad-pcb__get_project_info, mcp__kicad-pcb__set_board_size, mcp__kicad-pcb__add_layer, mcp__kicad-pcb__set_active_layer, mcp__kicad-pcb__get_board_info, mcp__kicad-pcb__get_layer_list, mcp__kicad-pcb__add_board_outline, mcp__kicad-pcb__add_mounting_hole, mcp__kicad-pcb__add_board_text, mcp__kicad-pcb__add_zone, mcp__kicad-pcb__get_board_extents, mcp__kicad-pcb__get_board_2d_view, mcp__kicad-pcb__place_component, mcp__kicad-pcb__move_component, mcp__kicad-pcb__rotate_component, mcp__kicad-pcb__delete_component, mcp__kicad-pcb__edit_component, mcp__kicad-pcb__find_component, mcp__kicad-pcb__get_component_properties, mcp__kicad-pcb__group_components, mcp__kicad-pcb__add_net, mcp__kicad-pcb__route_trace, mcp__kicad-pcb__add_via, mcp__kicad-pcb__add_copper_pour, mcp__kicad-pcb__set_design_rules, mcp__kicad-pcb__get_design_rules, mcp__kicad-pcb__run_drc |
PCB layout, component placement, and routing.
This skill activates when:
.kicad_pcb filesRequires:
hardware/*.kicad_sch - Completed schematic with netlistdocs/component-selections.md - Component detailsdocs/design-constraints.json - Board size, layer count, etc.datasheets/ - For placement/routing recommendationsProduces:
hardware/*.kicad_pcb - KiCad PCB filedocs/pcb-status.md - Layout progress tracking@docs/design-constraints.json
@docs/component-selections.md
@docs/schematic-status.md
@datasheets/ (for placement guidance)
Before starting layout, verify:
| Check | Source | Action if Missing |
|---|---|---|
| Schematic ERC clean | schematic-status.md | Complete schematic first |
| Layer count decided | design-constraints.json | See LAYER-COUNT-DECISION.md |
| Stackup selected | design-constraints.json | See STACKUP-DECISION.md |
| Board dimensions | design-constraints.json | Define constraints |
| Critical interfaces | design-constraints.json | USB, SPI speeds, etc. |
| Thermal budget | design-constraints.json | Power dissipation known |
Extract key constraints:
{
"board": {
"layers": 4,
"thickness": 1.6,
"dimensions": {"width": 50, "height": 40}
},
"dfmTargets": {
"manufacturer": "JLCPCB",
"minTraceWidth": 0.15,
"minClearance": 0.15,
"impedanceControl": true
},
"interfaces": {
"usb": true,
"highSpeedSpi": false
},
"thermal": {
"maxPowerDissipation": 2.5
}
}
Architecture Validation Warnings:
| Condition | Warning |
|---|---|
| USB + 2-layer board | Cannot achieve 90Ω impedance |
| Buck converter + no ground plane | EMI issues likely |
| WiFi/BLE + 2-layer | Antenna performance degraded |
| High-speed SPI (>20MHz) + long traces | Signal integrity risk |
| No thermal plan + >1W dissipation | Thermal issues likely |
Set rules appropriate for manufacturer:
JLCPCB standard:
- Min trace width: 0.127mm (5mil)
- Min clearance: 0.127mm (5mil)
- Min via drill: 0.3mm
- Min via annular ring: 0.13mm
Priority order:
See reference/PLACEMENT-STRATEGY.md for detailed guidelines.
Priority:
See reference/ROUTING-RULES.md for trace width and clearance guidelines.
Validation checklist before ordering:
| Category | Check | Reference |
|---|---|---|
| DRC | 0 errors, 0 warnings | DRC-VIOLATIONS-GUIDE.md |
| Clearances | Meet manufacturer minimums | DFM-RULES.md |
| Via sizes | Drill ≥ 0.3mm (JLCPCB std) | DFM-RULES.md |
| Annular rings | ≥ 0.13mm (1oz copper) | DFM-RULES.md |
| Trace widths | Power traces sized for current | ROUTING-RULES.md |
| USB traces | 90Ω impedance, length matched | HIGH-SPEED-ROUTING.md |
| Silkscreen | Not on pads, readable | Visual check |
| Board outline | Closed shape, proper clearance | DFM-RULES.md |
Thermal verification:
Signal integrity verification:
# PCB Layout Status
Project: [name]
Updated: [date]
## Board Specifications
- Size: X × Y mm
- Layers: N
- Thickness: 1.6mm
## Progress
- [x] Board outline defined
- [x] Mounting holes placed
- [x] Critical components placed
- [x] All components placed
- [ ] Power routing complete
- [ ] Signal routing complete
- [ ] Copper pours added
- [ ] DRC clean
## Layer Usage
| Layer | Usage |
|-------|-------|
| F.Cu | Signals, components |
| B.Cu | GND pour, some signals |
## DRC Status
- Errors: X
- Warnings: Y
- Unrouted nets: Z
## Design Rules
- Trace width: 0.2mm (signals), 0.5mm (power)
- Clearance: 0.2mm
- Via: 0.3mm drill, 0.6mm pad
## Notes
- [Any special considerations]
## Next Steps
- [What remains to be done]
| Document | Purpose |
|---|---|
reference/PLACEMENT-STRATEGY.md | Component placement guidelines |
reference/ROUTING-RULES.md | Trace width and routing rules |
reference/EMI-CONSIDERATIONS.md | EMI/EMC best practices |
reference/DFM-RULES.md | Design for manufacturing rules |
reference/DRC-VIOLATIONS-GUIDE.md | Common DRC errors and fixes |
reference/STACKUP-DECISION.md | Layer stackup selection |
reference/HIGH-SPEED-ROUTING.md | USB, SPI, I2C, antenna routing |
Upstream documents:
| Document | What to Extract |
|---|---|
LAYER-COUNT-DECISION.md (eda-architect) | Layer count rationale |
THERMAL-BUDGET.md (eda-architect) | Power dissipation limits |
DECOUPLING-STRATEGY.md (eda-research) | Cap values and placement |
SCHEMATIC-REVIEW-CHECKLIST.md (eda-schematics) | Pre-layout verification |
After PCB layout is complete:
/eda-check for comprehensive validationdesign-constraints.json stage to "validation"