Vitis HLS synthesis assistant for C/C++ to RTL conversion. Covers kernel development, pragma optimization, interface configuration, and synthesis report analysis. For post-synthesis implementation use vivado-impl, for timing analysis use vivado-analysis, for…
Use this skill when the user needs help with Vivado design analysis, timing report interpretation, or timing closure. This includes report_timing interpretation (slack calculation, path analysis, clock skew/uncertainty), report_timing_summary signoff…
Use this skill when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs. This includes clock definitions (create_clock, create_generated_clock, virtual clocks), I/O delay constraints (set_input_delay, set_output_delay,…
Use this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and…
Use this skill when the user needs help with Vivado implementation strategy selection and optimization. This includes opt_design (logic optimization directives and options), place_design (placement directives, congestion analysis, PSIP physical synthesis),…
Use this skill when the user needs help with Vivado simulation strategy, flow selection, and debugging. This includes behavioral simulation (RTL functional verification), post-synthesis simulation (netlist functional verification), post-implementation timing…
Use this skill when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synth_design option tuning, resource inference control (RAM/DSP/SRL/BRAM), hierarchy optimization (flatten_hierarchy, KEEP_HIERARCHY), OOC…
Use this skill when the user wants to generate, write, or execute Vivado/Vitis TCL scripts for FPGA design flows. This includes creating projects, running synthesis/implementation, programming devices, working with IP Integrator block designs, debug core…