stillwater-sc/kpu-sim

add-invariant

Add a new trace invariant (INV-XXX) to the LPDDR5 validation suite — documents it in INVARIANTS.md, implements the check in trace_validator.py, and wires it into validate(). Use when a new trace bug class is discovered and needs a permanent guard.

لغة النص الأصلي: الإنجليزية

lpddr5-trace-debug

Known LPDDR5 trace-generation bug classes and their fixes — wrong PRECHARGE txn_id, request type defaulting to WRITE, and tRCD/tRP/tRRD timing violations. Use when the trace validator reports INV-001/INV-002 violations or timing-constraint failures.

لغة النص الأصلي: الإنجليزية