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tilelang

النجوم٦٠

التفرعات١٠

آخر تحديث٣١ مايو ٢٠٢٦ في ٠٨:٥٧

TileLang DSL reference — the `@tilelang.jit` factory + `@T.prim_func` pattern, and the TileLang PDL binding (`T.pdl_trigger()` / `T.pdl_sync()`, with JIT auto-setting the launch attribute so no host-side flag is needed, unlike Triton). Use when writing or tuning a TileLang kernel, or wiring TileLang↔Triton PDL overlap.

التثبيت

التثبيت باستخدام Codex أو Claude انسخ هذا Prompt والصقه في Codex أو Claude أو مساعد آخر ليراجع صفحة Skill ويثبّتها لك.

تشغيل في Manus

المصدر

TongmingLAIC

TongmingLAIC/AKO4X

فتح مستودع GitHub عرض مستودعات المنشئ

تنزيل

تشغيل في Manus

المهن ذات الصلةSOC

استنادا إلى تصنيف SOC المهني

مطوّرو البرمجياتمهن الحاسوب والرياضيات·SOC 15-1252

مستكشف الملفات

2 ملفات

SKILL.md

readonly

name	tilelang
description	TileLang DSL reference — the `@tilelang.jit` factory + `@T.prim_func` pattern, and the TileLang PDL binding (`T.pdl_trigger()` / `T.pdl_sync()`, with JIT auto-setting the launch attribute so no host-side flag is needed, unlike Triton). Use when writing or tuning a TileLang kernel, or wiring TileLang↔Triton PDL overlap.

TileLang

Reference for TileLang kernel writers. Detailed guide: tilelang.md.

When to consult

Writing a TileLang kernel with T.pdl_trigger() / T.pdl_sync() for kernel→kernel overlap.
Verifying that JIT correctly sets the host launch attribute (no manual host-side flag needed in TileLang).
Picking pipeline depth / tile shapes for fused operators.

COUPLED references

None directly to runtime. Per-operator TileLang results / regressions live under docs/prior/ (when your operator has a prior archive) — note variant v12 in the dsa-sparse-attention archive for the PDL waves-per-SM threshold case.

المزيد من هذا المستودع

نفس المستودع

bench

TongmingLAIC/AKO4X

Run performance benchmarks to get a verdict on whether a kernel change actually helped. Use --ab-compare for sub-1x deltas (drift cancels in same container), --variance-check for noise floor, and the subset modes (--first, --smoke; --extremes is modal-backend only) for compile-correctness probes only — those are NOT performance verdicts. The only authoritative source for "is this change real". Benchmark specifics (config.toml schema, status enum, scoring formula, baseline rule, fresh-inputs contract) live in the `benchmark` skill.

2026-05-3160

benchmark

TongmingLAIC/AKO4X

Reference for the active benchmark harness — what it IS and how it behaves (the active benchmark is flashinfer-bench). Covers config.toml structure (`[solution]`/`[build]`/`[benchmark]` tables), the status enum, the workload / fresh-inputs model, reference-baseline + scoring mechanics, tolerance keys, TVM-FFI builder link limits, and the silent-skip cascade. Invoke whenever you decode a bench status string, hit an unfamiliar config.toml field, suspect "correctness passed but the headline is implausible", or need to know what's frozen before proposing a bench edit — do NOT guess field or status semantics. Bench commands and noise methodology (A/B compare, variance check, drift cancellation) live in the `bench` skill.

2026-05-3160

cpp

TongmingLAIC/AKO4X

Host-side C++ kernels (`[build].language = cpp`) — the `solution/{kernel.cpp, binding.py}` two-file TVM-FFI binding pattern, and when to reach for it (host-side orchestration of a kernel you write, or composing CUTLASS headers into it). Distinct from the `cuda` skill which covers `.cu` device kernels compiled by nvcc. Use when writing a host-side C++ kernel or deciding cpp-vs-cuda.

2026-05-3160

cuda

TongmingLAIC/AKO4X

CUDA C++ (.cu) kernel reference — TVM-FFI direct-export vs Python-binding entry points, the chevron-launch null-stream pitfall under CUDA-graph capture, the sm_100 fp8→bf16 cvt PTX gap, the load_inline name-cache trap, and the __launch_bounds__ register-spill lever. Also the single-source for generic per-call-overhead / CUDA-graph-capture / PDL theory (Waves-Per-SM decision table) regardless of DSL. Use when writing or debugging hand-written CUDA C++ kernels, or whenever you need generic CUDA-graph / sync-audit / PDL reasoning.

2026-05-3160

cute-dsl

TongmingLAIC/AKO4X

CuTe DSL reference — NVIDIA's CUTLASS Python DSL. Use whenever writing or debugging a CuTe DSL kernel — covers the `@cute.kernel` + `@cute.jit` + `.launch()` host pattern, `from_dlpack` tensor conversion, API-probing against the installed wheel, the launch-kwarg table, and the well-known graph-capture pitfall (CuTe's TVM-FFI stream binding does NOT pick up CUDA-graph capture mode — flashinfer-bench issue 414).

2026-05-3160

profiler-ncu

TongmingLAIC/AKO4X

Run NVIDIA Nsight Compute (NCU) per-kernel profiling for register pressure, occupancy, stall-reason, memory-throughput, and IPC analysis. Use BEFORE architecting an optimization fix — not only after — when a hypothesis about microarchitectural behavior needs verification. NCU `Duration` is NOT comparable to bench timing; use NCU for ratios only.

2026-05-3160

name	tilelang
description	TileLang DSL reference — the `@tilelang.jit` factory + `@T.prim_func` pattern, and the TileLang PDL binding (`T.pdl_trigger()` / `T.pdl_sync()`, with JIT auto-setting the launch attribute so no host-side flag is needed, unlike Triton). Use when writing or tuning a TileLang kernel, or wiring TileLang↔Triton PDL overlap.

TileLang

Reference for TileLang kernel writers. Detailed guide: tilelang.md.

When to consult

Writing a TileLang kernel with T.pdl_trigger() / T.pdl_sync() for kernel→kernel overlap.
Verifying that JIT correctly sets the host launch attribute (no manual host-side flag needed in TileLang).
Picking pipeline depth / tile shapes for fused operators.