القائمة
Analyze simulation failures by cross-referencing workspace artifacts and producing a structured debug report with fix suggestions.
التثبيت باستخدام Codex أو Claude انسخ هذا Prompt والصقه في Codex أو Claude أو مساعد آخر ليراجع صفحة Skill ويثبّتها لك.
استنادا إلى تصنيف SOC المهني
Run full Chipyard-to-ORFS PnR flow for large designs (SmallBOOM etc.) using All-Mock memory blackboxing in Docker: generate RTL, preprocess nosram, run multi-round ORFS synth->finish with mock SRAMs to avoid OOM.
Docker Chipyard flow: generate RTL from a Chipyard config via Docker, run SRAM mapping, stage artifacts into MyDesign, and hand off to PnR.
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration in Docker: generate RTL from Chipyard Docker, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal PPA.
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration: generate RTL from Chipyard with ENABLE_YOSYS_FLOW, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal PPA.
Unified Chipyard PnR flow: automatically routes to local or Docker workflow based on backend_mode setting.
Unified Chipyard flow: automatically routes to local or Docker workflow based on backend_mode setting.
| name | debug |
| description | Analyze simulation failures by cross-referencing workspace artifacts and producing a structured debug report with fix suggestions. |
| disable-model-invocation | true |
| allowed-tools | ["Bash","Read","Write","Grep","Glob"] |
Analyze simulation failures for a hardware module by cross-referencing its workspace artifacts.
/chip-agent:debug <ModuleName>
Extract the module name from $ARGUMENTS. If empty or blank, ask the user: "Which module should I debug? Please provide a PascalCase module name (e.g., ALU, Counter, SimpleRISCV)."
Validate the module name. Must be PascalCase (starts with uppercase letter, contains only alphanumeric characters). If invalid, ask the user to provide a valid PascalCase name.
Determine the project root directory by finding the nearest ancestor directory of this skill file that contains .claude. Store as PROJECT_ROOT.
Check required artifacts exist:
workspace/<ModuleName>/spec.json -- if missing, STOP: "No spec found. Run /chip-agent:requirement-parser first."chisel-project/src/main/scala/chipagent/<ModuleName>.scala -- if missing, STOP: "No Chisel source found for <ModuleName>."workspace/<ModuleName>/sim/logs/sim_result.log -- if missing, STOP: "No simulation results. Run /chip-agent:simulate <ModuleName> first."workspace/<ModuleName>/sim/logs/<ModuleName>.vcd -- if missing, note that VCD is unavailable. Analysis will proceed in log-only mode.Read the debug-analyzer agent definition at agents/debug-analyzer.md (relative to project root).
Follow the agent's analysis instructions to:
scripts/parse_vcd.pyWrite the debug report to workspace/<ModuleName>/debug/debug_report.md following the agent's report structure. Create the directory first with mkdir -p workspace/<ModuleName>/debug.
Display a summary in conversation:
workspace/<ModuleName>/debug/debug_report.md/chip-agent:simulate <ModuleName>."$ARGUMENTS -- PascalCase module name.
workspace/<ModuleName>/debug/debug_report.md -- structured failure analysis with signal traces, root cause analysis, and fix suggestions