Run any Skill in Manus with one click

transistor-models

Stars116

Forks22

UpdatedMarch 9, 2026 at 16:58

Complete PTM (Predictive Technology Model) MOSFET model library from mec.umn.edu/ptm, covering all nodes: bulk conventional 180/130/90/65nm, bulk HP/LP 45/32/22nm (BSIM4), and PTM-MG multi-gate FinFET 7/10/14/16/20nm (BSIM-CMG, HP + LSTP). No manual downloads required after installing this skill. Independent of the gmoverid skill — can be used directly in any ngspice/HSPICE project.

Installation

Install with Codex or Claude Copy this prompt, paste it into Codex, Claude, or another assistant, and let it review the skill page and install it for you.

Run Skill in Manus

Source

Arcadia-1

Arcadia-1/gmoverid-skill

View GitHub Repository View Creator Repositories

Download

Run Skill in Manus

Related occupationsSOC

Based on SOC occupation classification

Electrical EngineersArchitecture and Engineering Occupations·SOC 17-2071

File Explorer

34 files

SKILL.md

readonly

More from this repository

same repository

sky130-pdk

Arcadia-1/gmoverid-skill

Sky130A open PDK workflow for ngspice-based analog simulation. Use when an agent needs to install or locate Sky130A via Volare/open_pdks, run process-corner PVT simulations, run process Monte Carlo or mismatch-aware smoke tests, instantiate sky130_fd_pr devices, or validate Sky130A examples such as MOS Id-Vgs, ring oscillators, and five-transistor OTAs.

2026-07-07116

ngspice

Arcadia-1/gmoverid-skill

ngspice simulation tutorial and template skill. Provides nine standard simulation examples: (1) Transient — RC charging voltage and current; (2) DC — NMOS Id-Vds family curves; (3) AC — RC low-pass filter frequency response; (4) Noise — RC filter output noise spectral density and kT/C; (5) Transient — sample-and-hold switch comparison; (6) Transient — kT/C noise time-domain statistical measurement; (7) DC — NMOS current mirror output characteristics; (8) AC — common-source amplifier frequency response; (9) DC — transmission gate on-resistance. Built-in PTM 180/45/22nm models included.

2026-03-16116

gmoverid

Arcadia-1/gmoverid-skill

gm/ID transistor characterization and design methodology, based on ngspice + Python. Two independent workflows: (1) Characterization — generates three standard curve sets for any MOSFET model: gate capacitance (Cgg/Cgs/Cgd/Cgb vs Vgs), gm/ID four-quadrant characteristics (gm/Id vs Vov, Id/W vs gm/Id, fT vs gm/Id, gm·ro vs gm/Id), and IV characteristics (linear/log Id vs Vov, output curves). Supports 180 nm single-node and 45/22 nm HP multi-node flows with built-in PTM model files (180/45/22 nm) — no extra downloads required. (2) Design — the GmIdTable class builds a lookup table from simulation data (cached to logs/cache/) and provides lookup(), size(), size_from_ft(), size_from_gmro() APIs for NMOS/PMOS transistor sizing using the gm/ID methodology. Only depends on the ngspice skill. Use this skill when setting up or extending a gm/ID characterization project, generating characteristic curves, interpreting design curves, or sizing transistors by the gm/ID method.

2026-03-09116

name	transistor-models
description	Complete PTM (Predictive Technology Model) MOSFET model library from mec.umn.edu/ptm, covering all nodes: bulk conventional 180/130/90/65nm, bulk HP/LP 45/32/22nm (BSIM4), and PTM-MG multi-gate FinFET 7/10/14/16/20nm (BSIM-CMG, HP + LSTP). No manual downloads required after installing this skill. Independent of the gmoverid skill — can be used directly in any ngspice/HSPICE project.

Transistor Models Skill — Complete PTM Library

Important — do not modify skill files during normal use. When using models, copy the required .lib files into the user's project directory (outside .claude/). Do not modify or delete files inside the skill's assets/models/ directory. Only update the skill's internal files when the user explicitly asks to refresh the model library.

Source: All model files are from PTM — Arizona State University (ptm.asu.edu), free for academic research.

Citations:

Bulk CMOS nodes: W. Zhao and Y. Cao, "New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration," IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2816–2823, Nov. 2006. doi: 10.1109/TED.2006.884077
PTM-MG FinFET nodes: S. Sinha, G. Yeric, V. Chandra, B. Cline and Y. Cao, "Exploring sub-20nm FinFET design with Predictive Technology Models," DAC 2012, pp. 283–288. doi: 10.1145/2228360.2228414

Directory Structure

assets/models/
├── bulk_cmos/              — Bulk CMOS (BSIM3v3 / BSIM4)
│   ├── ptm180.lib          — 180nm conventional
│   ├── ptm130.lib          — 130nm conventional
│   ├── ptm90.lib           — 90nm conventional
│   ├── ptm65.lib           — 65nm conventional
│   ├── ptm45hp.lib         — 45nm HP
│   ├── ptm45lp.lib         — 45nm LP
│   ├── ptm32hp.lib         — 32nm HP
│   ├── ptm32lp.lib         — 32nm LP
│   ├── ptm22hp.lib         — 22nm HP
│   └── ptm22lp.lib         — 22nm LP
└── finfet/
    ├── models              — PTM-MG library entry point (.LIB ptm{n}hp / ptm{n}lstp)
    ├── param.inc           — Shared parameters (fin_height/fin_width/lg/vdd, per node)
    ├── hp/                 — HP nodes: {7,10,14,16,20}nfet.pm / pfet.pm
    └── lstp/               — LSTP nodes: {7,10,14,16,20}nfet.pm / pfet.pm

Model Reference

Bulk CMOS — Conventional (BSIM3v3/BSIM4, combined NMOS+PMOS)

File	Node	VDD	Model names
`bulk_cmos/ptm180.lib`	180nm	1.8V	`NMOS` / `PMOS`
`bulk_cmos/ptm130.lib`	130nm	1.3V	`nmos` / `pmos`
`bulk_cmos/ptm90.lib`	90nm	1.2V	`nmos` / `pmos`
`bulk_cmos/ptm65.lib`	65nm	1.1V	`nmos` / `pmos`

Bulk CMOS — HP/LP (BSIM4, combined NMOS+PMOS)

File	Node	Type	VDD	Model names
`bulk_cmos/ptm45hp.lib`	45nm	HP	1.0V	`nmos` / `pmos`
`bulk_cmos/ptm45lp.lib`	45nm	LP	1.1V	`nmos` / `pmos`
`bulk_cmos/ptm32hp.lib`	32nm	HP	0.9V	`nmos` / `pmos`
`bulk_cmos/ptm32lp.lib`	32nm	LP	1.0V	`nmos` / `pmos`
`bulk_cmos/ptm22hp.lib`	22nm	HP	0.8V	`nmos` / `pmos`
`bulk_cmos/ptm22lp.lib`	22nm	LP	1.0V	`nmos` / `pmos`

FinFET — PTM-MG Multi-Gate (BSIM-CMG)

Entry file: finfet/models — select node and type via .lib section tag:

Tag	Node	Type	VDD
`ptm20hp`	20nm	HP	0.9V
`ptm16hp`	16nm	HP	0.85V
`ptm14hp`	14nm	HP	0.8V
`ptm10hp`	10nm	HP	0.75V
`ptm7hp`	7nm	HP	0.7V
`ptm20lstp`	20nm	LSTP	0.9V
`ptm16lstp`	16nm	LSTP	0.85V
`ptm14lstp`	14nm	LSTP	0.8V
`ptm10lstp`	10nm	LSTP	0.75V
`ptm7lstp`	7nm	LSTP	0.7V

FinFET model names are nfet / pfet (subckt-wrapped); use NFIN to set the number of fins.

ngspice Usage

Loading a Bulk CMOS File

* Load 45nm HP (contains both nmos and pmos models)
.include "models/bulk_cmos/ptm45hp.lib"

* Instantiate NMOS
M1  drain  gate  source  bulk  nmos  W=1u  L=45n

Loading a PTM-MG FinFET

* Load 7nm HP FinFET
.lib "models/finfet/models" ptm7hp

* PTM-MG model names are nfet / pfet
* Use NFIN (number of fins) instead of W
M1  drain  gate  source  bulk  nfet  NFIN=1  L=7n

Model Type Quick Reference

Model	ngspice LEVEL	Applicable nodes	Notes
BSIM3v3	8	180nm–250nm	Mature bulk CMOS
BSIM4	54	65nm–22nm	Bulk HP/LP
BSIM-CMG	72	7nm–20nm	FinFET / multi-gate

Key Parameter Quick Reference

Parameter	Meaning	Typical range
`vth0`	Nominal threshold voltage [V]	NMOS: 0.3–0.5; PMOS: −0.5 to −0.3
`toxe`	Equivalent gate-oxide thickness [m]	1–4 nm (deep submicron)
`u0`	Low-field mobility [m²/Vs]	NMOS: 0.03–0.05; PMOS: 0.01–0.02
`vsat`	Saturation velocity [m/s]	1e5–2.5e5

Full parameter table in references/model_params.md.

Using a Custom PDK Model

If you have your own .lib file (foundry PDK or measured):

Copy it into the project models/ directory.
Find the .model name inside the file (e.g. .model mynmos NMOS level=54).
Instantiate using that name: M1 d g s b mynmos W=... L=...
Configure sweep ranges based on vth0, tox, etc.