@arm-cortex-expert workflow skill. Use this skill when the user needs Senior embedded software engineer specializing in firmware and driver development for ARM Cortex-M microcontrollers (Teensy, STM32, nRF52, SAMD) and the operator should preserve the upstream workflow, copied support files, and provenance before merging or handing off.
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@arm-cortex-expert workflow skill. Use this skill when the user needs Senior embedded software engineer specializing in firmware and driver development for ARM Cortex-M microcontrollers (Teensy, STM32, nRF52, SAMD) and the operator should preserve the upstream workflow, copied support files, and provenance before merging or handing off.
This public intake copy packages plugins/antigravity-awesome-skills/skills/arm-cortex-expert from https://github.com/sickn33/antigravity-awesome-skills into the native Omni Skills editorial shape without hiding its origin.
Use it when the operator needs the upstream workflow, support files, and repository context to stay intact while the public validator and private enhancer continue their normal downstream flow.
This intake keeps the copied upstream files intact and uses the external_source block in metadata.json plus ORIGIN.md as the provenance anchor for review.
@arm-cortex-expert
Imported source sections that did not map cleanly to the public headings are still preserved below or in the support files. Notable imported sections: 🎯 Role & Objectives, 🧠 Knowledge Base, 🛡️ Safety-Critical Patterns for ARM Cortex-M7 (Teensy 4.x, STM32 F7/H7), 🎯 Interrupt Priorities & NVIC Configuration, 🔒 Critical Sections & Interrupt Masking, 🐛 Hardfault Debugging Basics.
When to Use This Skill
Use this section as the trigger filter. It should make the activation boundary explicit before the operator loads files, runs commands, or opens a pull request.
Working on @arm-cortex-expert tasks or workflows
Needing guidance, best practices, or checklists for @arm-cortex-expert
The task is unrelated to @arm-cortex-expert
You need a different domain or tool outside this scope
Use when the request clearly matches the imported source intent: Senior embedded software engineer specializing in firmware and driver development for ARM Cortex-M microcontrollers (Teensy, STM32, nRF52, SAMD).
Use when the operator should preserve upstream workflow detail instead of rewriting the process from scratch.
Operating Table
Situation
Start here
Why it matters
First-time use
metadata.json
Confirms repository, branch, commit, and imported path through the external_source block before touching the copied workflow
Provenance review
ORIGIN.md
Gives reviewers a plain-language audit trail for the imported source
Workflow execution
SKILL.md
Starts with the smallest copied file that materially changes execution
Supporting context
SKILL.md
Adds the next most relevant copied source file without loading the entire package
Handoff decision
## Related Skills
Helps the operator switch to a stronger native skill when the task drifts
Workflow
This workflow is intentionally editorial and operational at the same time. It keeps the imported source useful to the operator while still satisfying the public intake standards that feed the downstream enhancer flow.
Clarify goals, constraints, and required inputs.
Apply relevant best practices and validate outcomes.
Provide actionable steps and verification.
If detailed examples are required, open resources/implementation-playbook.md.
Use @arm-cortex-expert-v2 to handle <task>. Start from the copied upstream workflow, load only the files that change the outcome, and keep provenance visible in the answer.
Explanation: This is the safest starting point when the operator needs the imported workflow, but not the entire repository.
Example 2: Ask for a provenance-grounded review
Review @arm-cortex-expert-v2 against metadata.json and ORIGIN.md, then explain which copied upstream files you would load first and why.
Explanation: Use this before review or troubleshooting when you need a precise, auditable explanation of origin and file selection.
Example 3: Narrow the copied support files before execution
Use @arm-cortex-expert-v2 for <task>. Load only the copied references, examples, or scripts that change the outcome, and name the files explicitly before proceeding.
Explanation: This keeps the skill aligned with progressive disclosure instead of loading the whole copied package by default.
Example 4: Build a reviewer packet
Review @arm-cortex-expert-v2 using the copied upstream files plus provenance, then summarize any gaps before merge.
Explanation: This is useful when the PR is waiting for human review and you want a repeatable audit packet.
Imported Usage Notes
Imported: 🛠 Example: SPI Driver for External Sensor
Pattern: Create non-blocking SPI drivers with transaction-based read/write:
STM32: HAL_SPI_Transmit() / HAL_SPI_Receive() or LL drivers
nRF52: nrfx_spi_xfer() or nrf_drv_spi_transfer()
SAMD: Configure SERCOM in SPI master mode with SERCOM_SPI_MODE_MASTER
Best Practices
Treat the generated public skill as a reviewable packaging layer around the upstream repository. The goal is to keep provenance explicit and load only the copied source material that materially improves execution.
Safety Over Performance: correctness first; optimize after profiling
Full Solutions: complete drivers with init, ISR, example usage — not snippets
Document Tradeoffs: blocking vs async, RAM vs flash, throughput vs CPU load
Troubleshooting
Problem: The operator skipped the imported context and answered too generically
Symptoms: The result ignores the upstream workflow in plugins/antigravity-awesome-skills/skills/arm-cortex-expert, fails to mention provenance, or does not use any copied source files at all.
Solution: Re-open metadata.json, ORIGIN.md, and the most relevant copied upstream files. Check the external_source block first, then restate the provenance before continuing.
Problem: The imported workflow feels incomplete during review
Symptoms: Reviewers can see the generated SKILL.md, but they cannot quickly tell which references, examples, or scripts matter for the current task.
Solution: Point at the exact copied references, examples, scripts, or assets that justify the path you took. If the gap is still real, record it in the PR instead of hiding it.
Problem: The task drifted into a different specialization
Symptoms: The imported skill starts in the right place, but the work turns into debugging, architecture, design, security, or release orchestration that a native skill handles better.
Solution: Use the related skills section to hand off deliberately. Keep the imported provenance visible so the next skill inherits the right context instead of starting blind.
Related Skills
@00-andruia-consultant - Use when the work is better handled by that native specialization after this imported skill establishes context.
@00-andruia-consultant-v2 - Use when the work is better handled by that native specialization after this imported skill establishes context.
@10-andruia-skill-smith - Use when the work is better handled by that native specialization after this imported skill establishes context.
@10-andruia-skill-smith-v2 - Use when the work is better handled by that native specialization after this imported skill establishes context.
Additional Resources
Use this support matrix and the linked files below as the operator packet for this imported skill. They should reflect real copied source material, not generic scaffolding.
Resource family
What it gives the reviewer
Example path
references
copied reference notes, guides, or background material from upstream
references/n/a
examples
worked examples or reusable prompts copied from upstream
examples/n/a
scripts
upstream helper scripts that change execution or validation
scripts/n/a
agents
routing or delegation notes that are genuinely part of the imported package
agents/n/a
assets
supporting assets or schemas copied from the source package
Rust: Use cortex_m::asm::dmb() and cortex_m::asm::dsb() around volatile reads/writes. Create macros like safe_read_reg!(), safe_write_reg!(), safe_modify_reg!() that wrap HAL register access.
Why This Matters: M7 reorders memory operations for performance. Without barriers, register writes may not complete before next instruction, or reads return stale cached values.
DMA and Cache Coherency
CRITICAL: ARM Cortex-M7 devices (Teensy 4.x, STM32 F7/H7) have data caches. DMA and CPU can see different data without cache maintenance.
Alignment Requirements (CRITICAL):
All DMA buffers: 32-byte aligned (ARM Cortex-M7 cache line size)
Buffer size: multiple of 32 bytes
Violating alignment corrupts adjacent memory during cache invalidate
MPU-configured Non-cacheable regions - Configure OCRAM/SRAM regions as non-cacheable via MPU
Cache Maintenance (Last resort - slowest)
Before DMA reads from memory: arm_dcache_flush_delete() or cortex_m::cache::clean_dcache_by_range()
After DMA writes to memory: arm_dcache_delete() or cortex_m::cache::invalidate_dcache_by_range()
Address Validation Helper (Debug Builds)
Best practice: Validate MMIO addresses in debug builds using is_valid_mmio_address(addr) checking addr is within valid peripheral ranges (e.g., 0x40000000-0x4FFFFFFF for peripherals, 0xE0000000-0xE00FFFFF for ARM Cortex-M system peripherals). Use #ifdef DEBUG guards and halt on invalid addresses.
Write-1-to-Clear (W1C) Register Pattern
Many status registers (especially i.MX RT, STM32) clear by writing 1, not 0:
uint32_t status = mmio_read(&USB1_USBSTS);
mmio_write(&USB1_USBSTS, status); // Write bits back to clear them
Common W1C:USBSTS, PORTSC, CCM status. Wrong:status &= ~bit does nothing on W1C registers.
Platform Safety & Gotchas
⚠️ Voltage Tolerances:
Most platforms: GPIO max 3.3V (NOT 5V tolerant except STM32 FT pins)
Use level shifters for 5V interfaces
Check datasheet current limits (typically 6-25mA)
Teensy 4.x: FlexSPI dedicated to Flash/PSRAM only • EEPROM emulated (limit writes <10Hz) • LPSPI max 30MHz • Never change CCM clocks while peripherals active
Rust:cortex_m::interrupt::free(|cs| { /* use cs token */ })
Best Practices:
Keep critical sections SHORT (microseconds, not milliseconds)
Prefer BASEPRI over PRIMASK when possible (allows high-priority ISRs to run)
Use atomic operations when feasible instead of disabling interrupts
Document critical section rationale in comments
Imported: 🐛 Hardfault Debugging Basics
Common Causes:
Unaligned memory access (especially on M0/M0+)
Null pointer dereference
Stack overflow (SP corrupted or overflows into heap/data)
Illegal instruction or executing data as code
Writing to read-only memory or invalid peripheral addresses
Inspection Pattern (M3/M4/M7):
Check HFSR (HardFault Status Register) for fault type
Check CFSR (Configurable Fault Status Register) for detailed cause
Check MMFAR / BFAR for faulting address (if valid)
Inspect stack frame: R0-R3, R12, LR, PC, xPSR
Platform Limitations:
M0/M0+: Limited fault information (no CFSR, MMFAR, BFAR)
M3/M4/M7: Full fault registers available
Debug Tip: Use hardfault handler to capture stack frame and print/log registers before reset.
Imported: 📊 Cortex-M Architecture Differences
Feature
M0/M0+
M3
M4/M4F
M7/M7F
Max Clock
~50 MHz
~100 MHz
~180 MHz
~600 MHz
ISA
Thumb-1 only
Thumb-2
Thumb-2 + DSP
Thumb-2 + DSP
MPU
M0+ optional
Optional
Optional
Optional
FPU
No
No
M4F: single precision
M7F: single + double
Cache
No
No
No
I-cache + D-cache
TCM
No
No
No
ITCM + DTCM
DWT
No
Yes
Yes
Yes
Fault Handling
Limited (HardFault only)
Full
Full
Full
Imported: 🧮 FPU Context Saving
Lazy Stacking (Default on M4F/M7F): FPU context (S0-S15, FPSCR) saved only if ISR uses FPU. Reduces latency for non-FPU ISRs but creates variable timing.
Disable for deterministic latency: Configure FPU->FPCCR (clear LSPEN bit) in hard real-time systems or when ISRs always use FPU.
Imported: 🛡️ Stack Overflow Protection
MPU Guard Pages (Best): Configure no-access MPU region below stack. Triggers MemManage fault on M3/M4/M7. Limited on M0/M0+.
Canary Values (Portable): Magic value (e.g., 0xDEADBEEF) at stack bottom, check periodically.
