| name | ecram-short-term-plasticity |
| description | Cross-layer device-circuit-system co-design framework for implementing short-term plasticity (STP) in neuromorphic hardware using non-equilibrium ECRAM dynamics. Transforms volatile ionic dynamics from device artifacts into computational resources. Use when studying: neuromorphic short-term plasticity, ECRAM synaptic devices, temporal information processing in spiking networks, delay-feedback LIF neurons, hardware-software co-design for neuromorphic circuits, or activity-dependent conductance modulation. arXiv: 2605.11243 (cs.NE, eess.SP). Currie, Borkholder, Manimaran, Han, Merkel, Xu, Das.
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ECRAM Short-Term Plasticity for Neuromorphic Circuits
Cross-layer device-circuit-system co-design that transforms non-equilibrium ECRAM
(Electrochemical RAM) volatile dynamics into a native hardware substrate for short-term
plasticity (STP) and temporal computation.
Source: arXiv 2605.11243v1 (2026-05-11), cs.NE, eess.SP
Core Problem
Short-term plasticity (STP) — facilitation and depression — is fundamental to temporal
information processing in biological neural systems but remains difficult to implement
efficiently in neuromorphic hardware. ECRAM memristive devices naturally exhibit non-equilibrium
ionic dynamics producing transient conductance modulation, but these are typically treated as
undesirable variability rather than computational resources.
Key Innovation
Transform volatile ECRAM device dynamics from a tolerated artifact into a computational resource
through cross-layer co-design, with negligible additional circuit overhead.
Architecture
Device Layer: ECRAM Transient Conductance
- ECRAM devices exhibit activity-dependent transient conductance modulation (~1.5 KΩ per spike)
- Non-equilibrium ionic dynamics produce time-varying conductance that decays back to baseline
- Compact behavioral model derived from experimentally characterized devices for circuit simulation
Circuit Layer: Delay-Feedback LIF Neuron
- LIF neuron with tunable delay-feedback spike-generation path
- ECRAM synapses directly modulate neuron excitability through transient conductance changes
- Two key STP behaviors emerge naturally:
- Synaptic facilitation: Transient conductance increase with repeated activation
- Intrinsic excitability modulation: Device-driven changes in neuron threshold dynamics
- Energy consumption: 2 pJ per spike
System Layer: Temporal Filtering in SNNs
- Individual ECRAM synapses act as tunable temporal filters within spiking neural networks
- Frequency-selective spike processing emerges from the device dynamics
- Mechanisms extend across multiple neuron topologies
Framework Workflow
Step 1: Device Characterization
Measure ECRAM conductance response to spike trains:
- Transient conductance change per spike (ΔG ≈ 1.5 KΩ/spike)
- Recovery time constant (τ_recovery)
- Activity dependence (frequency, spike count)
Step 2: Behavioral Model Development
Derive compact model suitable for circuit-level simulation:
- Capture non-equilibrium ionic dynamics
- Parameterize transient conductance modulation
- Validate against experimental device data
Step 3: Circuit Co-Design
Design delay-feedback LIF neuron architecture:
- Integrate ECRAM synapses into neuron input path
- Add tunable delay-feedback for spike generation
- Ensure transient dynamics modulate excitability
Step 4: System-Level Validation
Network-level analysis:
- Demonstrate frequency-selective spike processing
- Verify synaptic facilitation behavior
- Test across multiple neuron topologies
- Measure energy efficiency (target: ~2 pJ/spike)
Key Results
| Metric | Value |
|---|
| Energy per spike | 2 pJ |
| Conductance change | ~1.5 KΩ per spike |
| STP behaviors | Facilitation + intrinsic excitability modulation |
| Topology support | Multiple neuron architectures |
| Network function | Frequency-selective temporal filtering |
Comparison with Alternative Approaches
| Approach | STP Implementation | Overhead | Energy |
|---|
| ECRAM (this work) | Native device dynamics | Negligible | 2 pJ/spike |
| Digital emulation | Software lookup tables | High | Variable |
| Additional capacitors | Extra circuit components | Moderate | Higher |
| Phase-change memory | Programmed resistance states | High | Higher |
Activation Keywords
- ECRAM short-term plasticity, neuromorphic STP
- non-equilibrium ionic dynamics, transient conductance modulation
- delay-feedback LIF neuron, hardware temporal filtering
- cross-layer neuromorphic design, activity-dependent conductance
- memristive synaptic plasticity, energy-efficient neuromorphic
Tools Used
- ECRAM device characterization (experimental)
- Circuit-level simulation (compact behavioral models)
- Spiking neural network simulation (network-level analysis)
- Cross-layer co-design methodology
Applications
- Temporal pattern recognition: STP enables SNNs to process time-varying signals
- Event-based vision: Low-power temporal filtering for DVS cameras
- Auditory processing: Frequency-selective spike processing for cochlear implants
- Adaptive control: Activity-dependent plasticity for closed-loop systems
Pitfalls & Notes
- ECRAM device variability must be characterized before behavioral model development
- The framework assumes access to experimentally characterized ECRAM devices
- Recovery time constants vary by device fabrication — must be measured per batch
- The approach generalizes beyond ECRAM to any device with transient conductance dynamics
- Digital twin quality of the device model is critical for accurate circuit simulation
- Energy efficiency (2 pJ/spike) is specific to the reported device-circuit configuration
