hardware-codex-skills

Use this skill for freeze-grade hardware component decisions that need evidence reconciliation before a choice can be locked into schematic, BOM, pin assignment, layout, sourcing, or validation work. Trigger on critical component selection, BOM freeze review, EOL/PCN or supplier substitute decisions, candidate part-number decisions, shortlist review, vendor feedback against a requirement baseline, selection evidence map, procurement brief, supplier/FAE inquiry, leadership brief, 关键物料选型, BOM 冻结前评审, 选型证据地图, 选型报告, 沟通报告, or 候选料号决策. Common critical conditions include lifecycle/EOL/PCN/lead-time risk, toolchain verification such as EMIF/fitter/SI/PI/thermal, pinout/power/SI/thermal architecture impact, and vendor evidence that must be reconciled against requirements. Do NOT use for casual comparisons, learning questions, architecture sketches, or selections that do not require evidence reconciliation and freeze conditions.

Use only when the user requests a deliverable-grade pin/net assignment artifact in Excel/CSV form for OrCAD Capture, Cadence Capture CIS, or Allegro DE-HDL schematic drawing, including FPGA/SoC-to-memory or peripheral pin assignment workbooks, package ballout to schematic-symbol-order mapping tables, off-page connector lists for batch paste, and pin assignment audits against vendor official sources. Triggers include: pin assign 工作簿, 引脚分配表, 原理图顺序网名表, OrCAD off-page connector 表, 封装 ballout 映射, 管脚映射审核, schematic-order pin/net workbook, ballout-to-symbol mapping. Do NOT use for casual pin lookups, single datasheet questions, component or package selection, layout/SI/PI advice, FPGA toolchain constraint files such as QSF/XDC/LPF/SDC unless the user also asks for the Excel review surface, or requests without a concrete pin/net deliverable.