PDN DC voltage/current analysis, IR drop, design rule checking, and multi-net batch analysis on imported PCB layouts. TRIGGER: user asks about power integrity, PDN analysis, IR drop, voltage distribution, current density, power nets, or design rule checking on a PCB. Invoke BEFORE writing code — the PDN API chain is specialized and non-obvious. SKIP: importing a PCB file (use matlab-read-pcb-layout), EM field/S-parameter extraction (use matlab-analyze-em), material/stackup setup only (use matlab-manage-pcb-material), transmission line design (use matlab-design-pcb-transmission-line).
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PDN DC voltage/current analysis, IR drop, design rule checking, and multi-net batch analysis on imported PCB layouts. TRIGGER: user asks about power integrity, PDN analysis, IR drop, voltage distribution, current density, power nets, or design rule checking on a PCB. Invoke BEFORE writing code — the PDN API chain is specialized and non-obvious. SKIP: importing a PCB file (use matlab-read-pcb-layout), EM field/S-parameter extraction (use matlab-analyze-em), material/stackup setup only (use matlab-manage-pcb-material), transmission line design (use matlab-design-pcb-transmission-line).
pcbFileRead imports a PCB file and returns an object for hierarchical inspection. Supported formats: native directory (CSV files), ODB++ (zipped or unzipped), and Cadence Allegro .brd (requires one-time extractaSetup()).
% Native format (directory containing CSV files)
pcb = pcbFileRead(fullfile(boardDir, 'pcie5_native'));
% ODB++ format
pcb = pcbFileRead(fullfile(boardDir, 'myboard.zip'));
% Allegro .brd (run extractaSetup() once first)
extractaSetup(); % one-time setup for Allegro support
pcb = pcbFileRead(fullfile(boardDir, 'myboard.brd'));
The returned object exposes: NumLayers, NumCadnets, NumPadStacks, NumComponents, NumParts, LayerHeight.
Listing All Nets
NetList = cadnetList(pcb);
disp(NetList);
Returns a table with columns: CadnetIdx, CadnetName, NumPins, Length. A real board may have 3000+ nets.
Finding Power Nets
There is no built-in findPowerNets function. Filter the cadnetList output using regex to identify power and ground nets by name:
netList = cadnetList(pcb);
% Define naming patterns (case-insensitive)
powerPatterns = ["^P\d+V", "^VDD", "^VCC", "^AVDD", "^DVDD", "^VDDO"];
groundPatterns = ["^GND", "^AGND", "^DGND", "^PGND", "^VSS", "^AVSS", "^DVSS"];
% Match power nets
isPower = false(height(netList), 1);
for p = powerPatterns
isPower = isPower | ~cellfun(@isempty, regexpi(netList.CadnetName, p));
end
powerNets = sortrows(netList(isPower, :), 'NumPins', 'descend');
% Match ground nets
isGround = false(height(netList), 1);
for g = groundPatterns
isGround = isGround | ~cellfun(@isempty, regexpi(netList.CadnetName, g));
end
groundNets = sortrows(netList(isGround, :), 'NumPins', 'descend');
% Filter by minimum pin count
minPins = 5;
powerNets = powerNets(powerNets.NumPins >= minPins, :);
% Search for a specific pattern (e.g., 0.8V rails)
idx = ~cellfun(@isempty, regexpi(powerNets.CadnetName, "P0V8"));
rails_0v8 = powerNets(idx, :);
Common power net naming conventions (case-insensitive):
% Manual assignment using RefDes from findComponents
setNetworkParameters(PDN, ...
Source=sourceRefDes, ...
Load=sinkRefDes, ...
Sense=senseRefDes, ...
PlatingThickness=0.002);
% Auto-assign defaults (fallback when topology is unclear)
setNetworkParameters(PDN, AutoAssignDefault='True');
Source -- RefDes of the power source (typically an inductor). Use all inductors for multiphase rails.
Load -- RefDes of the load (typically an IC). Use all ICs on the net.
Sense -- RefDes of the sense component (typically a resistor or test point).
PlatingThickness -- Via barrel plating thickness in inches (e.g., 0.002 = 2 mil ≈ 1.4 oz copper).
Sense Component Resolution
The Sense parameter is required. When no test point is available on the net, use a resistor as the sense component:
tp = findComponents(cnet, 'ComponentType', 'Test Point');
if ~isempty(tp)
senseRef = tp.Refdes;
else
res = findComponents(cnet, 'ComponentType', 'Resistor');
senseRef = res.Refdes(1); % use first resistor as sense fallback
end
setNetworkParameters(PDN, Source=src, Load=load, Sense=senseRef, ...
PlatingThickness=0.002);
Multiphase Rails
For multiphase VRM designs, multiple inductors feed the same rail. Always use all inductors as Source, not just the first:
inferRailVoltage returns NaN for unrecognized nets. Guard with isnan() before using the result in calculations or display (e.g., string(NaN) produces "NaN", not missing).
Sense parameter is required in setNetworkParameters. When no test point exists on the net, use a resistor as the sense component. Omitting Sense will cause errors during analysis.
AutoAssignDefault is a fallback, not a first choice. It may produce incorrect topology assignments on complex rails (LDO, connector-fed). Prefer explicit assignment via findComponents output.
LoadCurrent cannot be inferred from board data — STOP and ask. Unlike NominalVoltage (which can be parsed from net names), load current must come from IC datasheets or system power budgets. Before calling setDCParameters, ask the user for the actual load current and STOP execution — do not proceed until the user responds. Do NOT assume 1 A or any default without explicit user confirmation. Once the user responds that they don't have it or asks you to proceed, present these estimation options and let them choose:
Per-pin heuristic: 0.5 A × number of load pins (e.g., 130 pins → 65 A)
TDP-based: total power budget ÷ rail voltage (e.g., 40 W ÷ 0.8 V = 50 A)
Fixed conservative: 10 A per load IC (quick screening)
1 A token: minimal value to verify the workflow runs end-to-end
Only after the user selects an option or provides a value, proceed with setDCParameters.
LoadCurrent must be a vector, not a scalar total. When multiple load ICs exist on a rail, setDCParameters requires one current value per load. For example, with loads U1 (4.8 A) and U9 (0.2 A): setDCParameters(PDN, LoadCurrent=[4.8, 0.2]). Passing a scalar (e.g., LoadCurrent=5) errors when the topology has more than one load.
PDN units are mixed — not all SI.PlatingThickness is in inches (not meters): 0.002 = 2 mil ≈ 1.4 oz copper. MaxCurrentDensity is mA/mil² (not A/mm²). MaxViaCurrent is mA (not A). MinVoltage/MaxVoltage are absolute volts. Using meters for plating (e.g., 35e-6) or amps for via current (e.g., 1) produces wildly incorrect results.
Batch mode: skip rather than block. When a rail is missing voltage, source, or load information, skip it and report which rails were skipped and why. Do not halt the entire batch for one incomplete rail.
Large boards have 3000+ nets.cadnetList returns all nets. Filter with regex on CadnetName to narrow to power/ground nets, then further filter by NumPins or specific patterns.
cnet.Voltage is unreliable. The Voltage property on the cadnet object is populated heuristically from the PCB file and often returns '0.000' even for valid power rails. Always parse the voltage from the net name using regex instead of relying on this property.
No built-in findPowerNets or inferRailVoltage. These do not exist as MATLAB functions. Use cadnetList(pcb) + regexpi filtering for net discovery, and the parseNetVoltage helper (defined in this skill) for voltage inference from net names.
.brd files require extracta — STOP if unavailable. If the user only has a .brd file and extractaSetup() returns [] or errors, STOP and inform the user: extracta (from a Cadence install) is required. Offer alternatives: (a) provide the path to extracta.exe, (b) export from Allegro as ODB++ or native CSV format, (c) use a colleague's Cadence install to convert. Do not attempt workarounds.
Related Skills
matlab-read-pcb-layout -- Importing PCB/package layouts for PDN analysis
matlab-manage-pcb-material -- Substrate and conductor material setup
matlab-model-via -- Via modeling for power delivery paths
