risc-v
RISC-V instruction set architecture and processor implementation
Source facts
- Repository
- NeuralBlitz/Mito
- Last source activity
- March 22, 2026 at 13:29
- Detected SKILL.md language
- English
- Stars
- 0
- Forks
- 0
Install options
The review-first prompt is selected by default. You can switch to a direct command or download a local copy.
Review the source files
Read SKILL.md and any companion files shown by SkillsMP before deciding whether to install.
Showing SKILL.md
SKILL.md
Source instructions · Read-only preview- name
- risc-v
- description
- RISC-V instruction set architecture and processor implementation
- license
- MIT
- compatibility
- opencode
- metadata
- {"audience":"students","category":"computer-hardware"}
## What I do
- Work with RISC-V ISA
- Design RISC-V processors
- Implement custom extensions
- Verify RISC-V implementations
## When to use me
When working on RISC-V processors or open-source hardware.
## Key Concepts
- RISC-V instruction formats
- Base and extension ISA
- Privilege modes
- RISC-V privileged spec
- Rocket Chip
- SiFive cores
- Custom extensions
View on GitHub