sancovp/concurrency-synchronization-primitives-a-module

0-1-1-understand-synchronizes-with

[0.1.1] A relation between atomic operations in memory models where a release fence on one thread synchronizes with an

0-1-2-understand-memory-order-relaxed

[0.1.2] C11/C++11 memory ordering that only guarantees atomicity of the operation with no ordering constraints relativ

0-1-3-understand-sequentially-consistent

[0.1.3] The strongest memory ordering requiring a single total order of all sequentially consistent operations visible

0-1-4-understand-acquire-semantics

[0.1.4] Memory ordering semantics ensuring all subsequent loads/stores cannot be reordered before the acquire operatio

0-1-5-understand-happens-before-relation

[0.1.5] A fundamental ordering relation in memory models defining that if operation A happens-before operation B, then

0-1-6-understand-c11-memory-model

[0.1.6] Standard C11 specification defining memory orderings: memory_order_relaxed, memory_order_consume, memory_order

0-2-1-understand-atomic-cas

[0.2.1] Compare-and-swap operation atomically loading a value, comparing it to an expected value, and storing a new va

0-2-2-understand-hb-synchronizes-with

[0.2.2] A synchronization operation or primitive that establishes an inter-thread happens-before relationship, ensurin

0-2-3-understand-atomic-exchange

[0.2.3] Atomic operation that reads the current value of a variable and writes a new value in a single indivisible ste

0-2-4-understand-cache-alignment

[0.2.4] Placement of data structures on memory boundaries matching cache line size, typically 64 bytes, preventing fal

0-3-1-understand-memory-order-relaxed-atomicity-guarantee

[0.3.1] The indivisibility guarantee that a relaxed atomic operation completes as a single indivisible step; no interm

0-3-2-understand-indivisibility-property

[0.3.2] The fundamental property that a relaxed atomic operation executes as a single indivisible step from the perspe

0-3-3-understand-memory-order-relaxed-vs-acquire

[0.3.3] The ordering contrast where acquire_semantics prevents subsequent operations from being reordered before the a

0-3-4-understand-seq-cst-global-total-order

[0.3.4] A single total order of all sequentially consistent operations that is visible and agreed upon by all threads

0-3-5-understand-rlx-atomicity-core

[0.3.5] The fundamental indivisibility property that any relaxed atomic operation completes as a single non-interrupti

0-3-6-understand-seq-cst-default-atomic-ordering

[0.3.6] The default memory ordering for std::atomic operations in C11/C++11 when no memory_order is explicitly specifi

0-3-understand-deep-c11-memory-model

[0.3] the deep_c11_memory_model subdomain of concurrency synchronization primitives and memory models (108 concepts)

0-4-1-understand-thundering-herd-contention-surge

[0.4.1] A transient spike in the rate of lock or resource acquisition attempts triggered by mass wakeup, producing que

0-4-2-understand-djt-bounding-range

[0.4.2] The closed interval [min_delay, previous_delay times decorrelation_factor] from which the uniform random sampl

0-4-3-understand-djt-random-uniform-sample

[0.4.3] The uniform random draw within the bounding range that produces the new current_delay value; the randomness de

0-4-4-understand-djt-wave-attenuation

[0.4.4] The emergent property that decorrelated jitter reduces the probability of simultaneous retries among competing

0-4-5-understand-thundering-herd-retry-coordination

[0.4.5] The phenomenon where concurrently woken threads retry a failing operation in near-lockstep, reinforcing the co

0-4-6-understand-thundering-herd-wait-set

[0.4.6] A collection of threads blocked on a single synchronization point awaiting a condition; the structural prerequ

0-5-1-understand-acquire-fence

[0.5.1] A memory ordering primitive that ensures all load and store operations appearing after the fence in program or

0-5-2-understand-hb-program-order

[0.5.2] The order of operations as they appear in source code within a single thread; a fundamental component of happe

0-5-3-understand-inter-thread-happens-before

[0.5.3] The subset of happens_before relations that cross thread boundaries, established by synchronizes_with connecti

0-5-4-understand-happens-before-order

[0.5.4] A transitive, irreflexive partial order over operations in a memory model that defines which operations must a

0-5-5-understand-hb-acquire-semantics

[0.5.5] A memory ordering guarantee where all subsequent memory operations become visible only after the acquire opera

0-5-6-understand-hb-release-semantics

[0.5.6] A memory ordering guarantee where all prior memory operations become visible before the release operation; pai

0-6-1-understand-rmw-ind-001

[0.6.1] rmw_operation: an atomic fetch_add, fetch_sub, fetch_or, fetch_and, fetch_xor, fetch_max, fetch_min, or fetch_

0-6-2-understand-isi-operation-completeness

[0.6.2] The property that a relaxed atomic operation executes to full completion before any observer can witness its e

0-6-3-understand-isi-no-in-flight-state

[0.6.3] The guaranteed absence of any transient value during operation execution that could be sampled by a concurrent

0-6-4-understand-rmw-ind-006

[0.6.4] modification_order_commitment: the serialization of the RMW operation into the global modification order of th

0-6-5-understand-rmw-ind-003

[0.6.5] modify_phase: the purely computational step wherein the value captured in the read phase is transformed by the

0-6-6-understand-rmw-ind-004

[0.6.6] write_phase: the final step wherein the result of the modify phase is written atomically to the target variabl

0-6-understand-deep-indivisibility-prope

[0.6] the deep_indivisibility_prope subdomain of concurrency synchronization primitives and memory models (19 concepts)

0-7-1-understand-jitter

[0.7.1] Randomized variance introduced into the computed delay to decorrelate competing threads and mitigate thunderin

0-7-2-understand-current-delay

[0.7.2] The computed wait interval for the current retry iteration; derived from base_delay multiplied by backoff_mult

0-7-3-understand-mcs-lock-enqueue

[0.7.3] Operation appending a thread-local qnode to the queue tail; atomically CASes qnode into tail; on CAS failure,

0-7-4-understand-base-delay

[0.7.4] Initial wait time in nanoseconds or microseconds before the first lock acquisition retry; the starting point o