together2329/brian_hw

oag-authoring-packet

Use before locked OAG RTL, TB, or evidence implementation dispatch when role-specific generated authoring packets must be compiled, audited, or passed to native subagents instead of raw user prose.

oag-contract-projection

Use when OAG requirements or requirement atoms must be projected into independently checkable obligations and assume/guarantee contracts with behavior, cycle, scenario, scoreboard, assertion, or coverage proof refs.

oag-decision-matrix

Use when OAG hardware IP work needs lock-blocking product or design choices captured, seeded from a profile, audited, or kept separate from locked truth before requirements, RTL, TB, or closure.

oag-deep-semantic-intake

Use when a compressed hardware IP request or spec note must be decomposed into source claims, hidden implications, ambiguity rows, and lock-blocking decision candidates before requirements, RTL, or TB work.

oag-evidence-closure

Use when OAG simulation, scoreboard, coverage, assertion, formal, validation, gate, or completion evidence must be audited for freshness, traceability, proof strength, and closure readiness.

oag-ip-workflow

Use when working on hardware IP requirements, RTL, testbench, simulation, coverage, signoff, common design-rule review, or evidence review through the Ontology Agent Gateway. Calls OAG before acting, records ROCEV-backed findings with explicit validation…

oag-ip-workflow

Use when working on hardware IP requirements, RTL, testbench, simulation, coverage, signoff, common design-rule review, or evidence review through the Ontology Agent Gateway. Calls OAG before acting, records ROCEV-backed findings with explicit validation…

ip-dev-memory

Keep an IP development session resumable by initializing <ip>/wiki and <ip>/.git, logging stage decisions, and committing IP-local snapshots.

ip-rocev-mini-run

Walk one hardware IP through Requirement, Obligation, Contract, Evidence, and Validation. Use for concise IP evidence demos and seminar examples.

rocev-evidence-review

Review a hardware completion claim against real artifacts. Use when the user asks whether RTL, TB, sim, coverage, VCD, formal, or signoff evidence is enough.

rocev-ip-audit

Audit multiple hardware IP directories for ROCEV evidence coverage. Use when the user asks to check many IPs, compare evidence quality, or build seminar examples from local artifacts.

ip-dev-memory

Keep an IP development session resumable by initializing <ip>/wiki and <ip>/.git, logging stage decisions, and committing IP-local snapshots.

ip-rocev-mini-run

Walk through any hardware IP using ROCEV. Use for seminar demos or short explanations of Requirement, Obligation, Contract, Evidence, and Validation.

rocev-evidence-review

Review one hardware task using Requirement -> Obligation -> Contract -> Evidence -> Validation. Use when the user asks whether RTL/TB/sim/formal evidence is enough, or asks why a PASS is trustworthy.

rocev-chain

Drive one IP through req → rtl → tb → sim with the ROCEV spine (Requirement → Obligation → Contract → Evidence → Validation) closed at every stage. Use when the user asks to take requirements to simulated RTL, or mentions ROCEV / obligation closure /…

ip-wiki

Maintain the per-IP wiki under <ip>/wiki — init the skeleton, append dated history entries while developing, create design pages, and gate frontmatter/link integrity. Use whenever finishing a stage, making a design decision, or hitting a gotcha on an IP.

rtl-to-signoff

Execute or plan the real ATLAS RTL-to-signoff flow from RTL disk checks through TB, sim, lint, coverage, synthesis, STA, PnR, and post-route STA. Use when the user asks for RTL to SignOff, RTL signoff, or full hardware closure.

external-db

External reference-database expert. Before authoring new RTL — or answering from assumed knowledge — consult the configured external DB for proven, authoritative references instead of reinventing. The DB is typically a prior-project / vendor RTL corpus (e.g.…

import

Import requirement documents, notes, existing RTL, or legacy YAML into ssot-gen evidence before grill-me/to-ssot. Use when the user wants to build SSOT from IP docs or existing RTL without hand-authoring the SSOT directly.

to-ssot

Synthesize the current conversation context (and codebase understanding) into a canonical SSOT YAML, including function_model and cycle_model, and write it to <ip>/yaml/<ip>.ssot.yaml. Use when the user wants to convert a finished discussion or grill-me…

grill-me

Sweep the SSOT for every TBD / unknown / null / missing-required field and capture each human decision through ATLAS QA tools. Use ask_user for immediate blockers and record_ssot_qa for deferred Review cards, so both paths appear as pending/approved in QA…

git

Git version control operations: 히스토리 조회, 파일 복구(revert), diff 확인. 이 agent는 write/replace 계열 파일 변경 실행 시 자동으로 git add + commit을 수행함 (GIT_VERSION_CONTROL_ENABLE=true, .config에서 설정). Trigger on: 'revert', 'undo', '이전 버전', '되돌려', 'git log', 'git history',…

Source text: Korean

pcie-expert

PCIe 7.0 spec expert. Covers TLP/DLLP packet structure, LTSSM state machine, Flow Control, Lane Equalization, Power Management, AER, ACS, TDISP, IDE, ATS, IOV, Physical/Data Link/Transaction Layer, Flit Mode, Link Training, Virtual Channel, Root Complex,…

testbench-expert

Verilog 테스트벤치 작성, 시뮬레이션 실행, 디버깅 시 호출. Trigger on: 'testbench', 'tb', 'simulation', 'iverilog', 'vvp', 'assert', 'stimulus', 'waveform', '시뮬레이션', '검증'.

Source text: Korean

nvme-expert

NVMe (Non-Volatile Memory Express) Base Spec 2.3 관련 모든 질문 시 호출. Command Set, Admin Commands, I/O Commands, Queue Model, Submission/Completion Queue, Namespace, Controller, PCIe Transport, Fabrics, NVM Command Set, Zoned Namespace, Key Value, Power Management,…

Source text: Korean

ucie-expert

UCIe (Universal Chiplet Interconnect Express) 스펙 관련 모든 질문 시 호출. Die-to-Die interface, Physical Layer, Die Adapter, Protocol Layer, FDI/RDI interface, Streaming Protocol, CXL over UCIe, PCIe over UCIe, Link Training, Parameter Exchange, Advanced/Standard…

Source text: Korean

spec-builder

새로운 스펙 PDF를 expert skill로 변환. PDF → markdown 계층 분해 → {spec}_index.json 생성 → spec_navigate 도구로 즉시 탐색 가능. UCIe/NVMe/기타 스펙 추가 시 호출. Trigger on: 새 스펙 추가, PDF를 스킬로, create expert, add spec, new spec skill.

Source text: Korean

verilog-expert

.v/.sv 파일 수정, RTL 신호 추적, FSM 분석, 합성 에러 수정 시 호출. Trigger on: 'verilog', 'module', 'signal', 'fsm', 'synthesis', 'rtl', 'always', 'wire', 'reg', 'posedge', '합성', '신호', '상태머신'.

Source text: Korean

code-analysis-expert

코드베이스 탐색, 정의 찾기, 함수/신호 추적, 코드 구조 분석. 특정 함수/클래스/심볼 위치 파악, 사용처 추적, call hierarchy 파악. Trigger on: 'find usage', 'trace', '어디에 있어', '코드 구조', 'call hierarchy', 'definition', '함수 찾아', '클래스 찾아'. NOTE: 파일 전체 내용/구조 파악(함수 목록 등)은 large-file-analyst를 사용할 것.

Source text: Korean

large-file-analyst

1000줄 이상 파일의 전체 내용/구조 파악 시 호출. 병렬 explore 에이전트로 1000줄씩 분할 스캔하여 빠르게 필요한 정보를 추출. Trigger on: '파일 전체 분석', '전체 구조', '함수 목록', '클래스 목록', '전체 내용', '파일 구조 파악', 'large file', '대용량 파일', '소스 전체', '코드 전체 분석'.

Source text: Korean