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Showing SKILL.md
| name | functional-verification |
| description | > Use when this capability is needed. |
When this skill is loaded and a user presents a verification task, do not
execute stages directly. Immediately spawn the
digital-chip-design-agents:verification-orchestrator agent and pass the full
user request and any available context to it. The orchestrator enforces the stage
sequence, loop-back rules, and sign-off criteria defined below.
Use the domain rules in this file only when the orchestrator reads this skill mid-flow for stage-specific guidance, or when the user asks a targeted reference question rather than requesting a full flow execution.
Before executing or advising on any stage, read the following files if they exist:
memory/verification/knowledge.md — known failure patterns, successful tool flags, PDK/tool quirks.
Incorporate its guidance into every stage decision. If absent, proceed without it.memory/verification/run_state.md — current run identity (run_id, design_name, tool,
last_stage). Use this to resume correctly after interruption. If absent, a new run
is starting; the orchestrator will create this file before the first stage.This pre-run read applies whether this skill is loaded by a user or called by the orchestrator mid-flow. It ensures the fix database is consulted before any diagnosis step.
Guide the complete UVM functional verification flow from testbench architecture through coverage-closed regression sign-off. Produces a verified RTL package with documented coverage and a clean regression.
verilator) — fast cycle-accurate simulator; UVM support via verilator+UVMiverilog) — event-driven simulation for quick testbench checkspip install cocotb)vcs) — industry-standard SV/UVM simulatorxrun) — multi-language simulator with coverage enginevsim / vlog / vcom) — mixed-language simulation with UVM supportuvm_test
└─ uvm_env
├─ agent_A (active) driver + monitor + sequencer
├─ agent_B (passive) monitor only
├─ scoreboard
├─ coverage_collector
└─ virtual_sequencer
feature_id: F001
description: AXI write burst handling
tests: [direct_single_write, burst_len_256, narrow_transfer]
assertions: [axi_valid_stable, axi_handshake_check]
covergroups: [burst_len_cg, burst_type_cg]
priority: P0
fix_request entry to design_state.fix_requests[] per the schema in the verification-orchestrator Design State section; terminate with decision=escalate. The pipeline-orchestrator (chip-design-meta) handles RTL re-invocation — do not loop locally or wait for user confirmation.| Type | Target | Priority |
|---|---|---|
| Functional (V-plan) | design_state.constraints.coverage.functional_pct% (default: 100%) | P0 |
| Code Line | ≥ design_state.constraints.coverage.line_pct% (default: 95%) | P1 |
| Code Branch | ≥ design_state.constraints.coverage.branch_pct% (default: 90%) | P1 |
| Code Toggle | ≥ design_state.constraints.coverage.toggle_pct% (default: 85%) | P2 |
| FSM State | design_state.constraints.coverage.fsm_state_pct% (default: 100%) | P0 |
| FSM Transition | ≥ design_state.constraints.coverage.fsm_transition_pct% (default: 95%) | P0 |
| Assertion triggered | design_state.constraints.coverage.assertion_pct% (default: 100%) | P1 |
| Tier | Trigger | Duration | Contents |
|---|---|---|---|
| Smoke | Every RTL commit | < 30 min | P0 directed tests |
| Nightly | Every night | < 8 hr | All directed + 100 random seeds |
| Weekly | Weekly gate | < 48 hr | Full suite, 1000 seeds |
| Sign-off | Tape-out gate | Unlimited | Full suite, 10,000 seeds |
coverage_analysis targets; driven by design_state.constraints.coverage.*)See plugins/meta/skills/pipeline-orchestration/SKILL.md §Constraints Schema for the authoritative schema and stage-entry validation rule.
No required keys for functional verification — all constraints in this domain are optional with schema defaults.
Optional (schema defaults apply when absent):
constraints.coverage.functional_pct (default: 100) — functional/V-plan coverage target %constraints.coverage.line_pct (default: 95) — code line coverage target %constraints.coverage.branch_pct (default: 90) — code branch coverage target %constraints.coverage.toggle_pct (default: 85) — toggle coverage target %constraints.coverage.fsm_state_pct (default: 100) — FSM state coverage target %constraints.coverage.fsm_transition_pct (default: 95) — FSM transition coverage target %constraints.coverage.assertion_pct (default: 100) — assertion trigger coverage target %Tag constraint_ref in history entries when evaluating QoR against these values (e.g. "coverage.functional_pct").
After each stage completes (regardless of whether an orchestrator session is active),
write or overwrite one JSON record in memory/verification/experiences.jsonl keyed by
run_id. This ensures data is persisted even if the flow is interrupted or called
without full orchestrator context.
Use run_id = verification_<YYYYMMDD>_<HHMMSS> (set once at flow start; reuse on each
stage update). Set signoff_achieved: false until the final sign-off stage completes.
Write memory/verification/run_state.md as the first action before launching any tool:
run_id: verification_<YYYYMMDD>_<HHMMSS>
design_name: <design>
tool: <primary tool>
start_time: <ISO-8601>
last_stage: <first stage name>
Update last_stage after each stage completes. This file lets wakeup-loop prompts
and resumed sessions identify the correct run without relying on in-memory state.
Create the file and parent directories if they do not exist.
If mcp__plugin_ecc_memory__add_observations is available in this session, emit each
applied fix as an observation to entity chip-design-verification-fixes after writing to
experiences.jsonl. Skip silently if the tool is absent — JSONL is the canonical record.
Source: chuanseng-ng/digital-chip-design-agents — distributed by TomeVault.