research-thermoelectric-semiconductors

name

research-thermoelectric-semiconductors

description

Route and execute rigorous thermoelectric semiconductor and device research, including field mapping, transport-physics reasoning, literature audits, hypotheses, experiment design, metrology, uncertainty, materials-to-device translation, and failure analysis; use for broad thermoelectric questions spanning materials, contacts, modules, cooling, or power generation, and route flexible Bi2Te3 or GeTe work to their dedicated Skills.

Research Thermoelectric Semiconductors

Build falsifiable, evidence-traceable research from transport physics to a working device. Treat peak material zT as one link, never as proof of useful device performance.

Route the task

• Use this Skill for broad field maps, proposals, experiment plans, mechanism audits, metrology, contacts, modules, cooling, and material-to-device translation.
• Activate develop-flexible-bismuth-telluride for bendable/conformal Bi2Te3-family films, composites, or wearable devices.
• Activate engineer-gete-thermoelectrics for GeTe chemistry, phase transition, defects, contacts, legs, or modules.
• Read foundations.md for equations, units, coupling, and device translation.
• Read research-methodology.md before designing experiments or diagnosing results.
• Read evidence-and-reporting.md before comparing papers, values, or device claims.

Frame the question

Write six items first: function; hot/cold boundary conditions; material/film/leg/module scale; controllable variables; primary observables; and a result that supports, weakens, or falsifies the hypothesis. Reject “raise zT” until temperature window, carrier type, process, geometry, and device target are defined.

Build this chain without skipping links:

chemistry/process → phase + defects + texture + interfaces → carriers + phonons → S, sigma, kappa versus T → contacts/legs → module → system value

For every mechanism, report intervention, predicted structural change, independent discriminator, predicted transport signature, confounders, control, and falsification condition.

Use stage gates

1. Reproduce a credible baseline and quantify batch variance.
2. Screen one mechanistic axis or a justified factorial design.
3. Connect verified chemistry/structure to independent transport observables.
4. Repeat the winner in independent batches through the service window.
5. Build junction, leg, or device coupons and measure actual operating temperatures and load curves.
6. Stress under relevant temperature, atmosphere, current, thermal cycling, and mechanics.

Combine S, sigma, and kappa into zT only for the same material state, direction, temperature, and equivalent specimens. Preserve raw dimensions, density, calibration, fitting assumptions, specimen identity, and uncertainty.

Deliver decisions

Return the smallest useful artifact: field map; hypothesis/DoE matrix; claim–evidence audit; symptom/cause/discriminator diagnosis; or device translation plan. End with what is measured, what is inferred, what is unknown, the next decisive experiment, and the stopping rule.

Never infer efficiency from peak zT, lattice thermal conductivity from an unjustified Lorenz number, scalability from a process label, or device value from coupon power factor alone.