lint_agent

Use for cross-level Verilog lint root-cause analysis from prepared RTL, slices, and filelist inputs.

Use this skill when the user provides Verilog/SystemVerilog source files or a source directory plus a top module, and wants a concise Chinese JSON diagnosis for hierarchical constant-propagation defects caused by parent-module constant pins or named wires that pollute child-module inputs, internal wires, and outputs across multiple levels, using the bundled trace_constant_propagation.py engine and then separating likely real defects from design-intended constants.

Use this skill when the user provides Verilog/SystemVerilog source files or a source directory plus a top module, and wants a concise Chinese JSON diagnosis for unreachable procedural branches, static dead-code conditions, or logic that disappears before/after Yosys proc/opt, especially cases where for-loop unfolding or constant loop variables make if/case branches impossible.

Use this skill when the user provides Verilog/SystemVerilog source files and a lint report, and wants the lint rows first pre-grouped by same source line and same violation description, then triaged into severe defect, general defect, or false positive, plus missed-defect discovery mapped to rules in the built-in custom knowledge base under skills/verilog-lint-triage/references, while batching IEEE standard lookups by semantic topic instead of per lint row, plus a separate standards-based code-only diagnosis section grounded in IEEE built-in references, with the final result written to a timestamped JSON file.

Use this skill when the user provides Verilog/SystemVerilog code plus a lint warning and wants a specific, code-aware repair recommendation in a concise Chinese JSON report rather than a generic lint-tool message, especially incomplete case coverage warnings such as W69 where the agent must identify missing case items or propose a concrete default branch.