Jeden Skill in Manus ausführen
mit einem Klick

Jeden Skill in Manus mit einem Klick ausführen

vivado-ip

Sterne3

Forks0

Aktualisiert22. April 2026 um 23:03

Create, configure, generate, and upgrade Xilinx IP cores. Use when instantiating IP catalog cores, configuring AXI interconnects, generating IP targets, handling OOC synthesis, upgrading stale IPs, or building block designs.

Installation

Mit Codex oder Claude installieren Kopieren Sie diesen Prompt, fügen Sie ihn in Codex, Claude oder einen anderen Assistant ein und lassen Sie die Skill-Seite prüfen und installieren.

In Manus ausführen

Quelle

devansh0703

devansh0703/vivaclaw-agent

GitHub-Repository öffnen Creator-Repositorys ansehen

Download

In Manus ausführen

Verwandte BerufeSOC

Basierend auf der SOC-Berufsklassifikation

SoftwareentwicklerInformatik- und Mathematikberufe·SOC 15-1252

SKILL.md

readonly

name	vivado-ip
version	1.0.0
description	Create, configure, generate, and upgrade Xilinx IP cores. Use when instantiating IP catalog cores, configuring AXI interconnects, generating IP targets, handling OOC synthesis, upgrading stale IPs, or building block designs.
metadata	{"openclaw":{"requires":{"bins":["vivado"]},"emoji":"📦"}}

Vivado IP Runbook

1. IP Creation & Config

create_ip -name <core_name> -vendor xilinx.com -library ip -module_name <inst_name>
set_property CONFIG.PARAM_NAME <value> [get_ips <inst_name>]
generate_target all [get_ips <inst_name>]

2. IP Status Audit

foreach ip [get_ips] {
  set status [get_property IP_INTEGRATION_STATUS $ip]
  set locked [get_property IS_LOCKED $ip]
  puts "IP: $ip | Status: $status | Locked: $locked"
}

3. Upgrade Flow

report_ip_status -file /tmp/vivaclaw_rpt/ip_status.rpt
upgrade_ip [get_ips -filter {UPGRADE_AVAILABLE == 1}]

4. Block Design (BD) Basics

create_bd_design "system"
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_intercon
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/cpu/M_AXI" }  [get_bd_intf_pins axi_intercon/S00_AXI]
validate_bd_design
save_bd_design

5. License Check

get_property IS_EVALUATION [get_ips <inst_name>]

Warning: Evaluation IPs produce bitstreams that expire after a few hours of hardware operation.

Mehr aus diesem Repository

gleiches Repository

vivado-flow

devansh0703/vivaclaw-agent

Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.

2026-04-223

vivado-cdc

devansh0703/vivaclaw-agent

Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.

2026-04-223

vivado-constraints

devansh0703/vivaclaw-agent

Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.

2026-04-223

vivado-debug

devansh0703/vivaclaw-agent

Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.

2026-04-223

vivado-floorplan

devansh0703/vivaclaw-agent

Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.

2026-04-223

vivado-flow

devansh0703/vivaclaw-agent

Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.

2026-04-223

name	vivado-ip
version	1.0.0
description	Create, configure, generate, and upgrade Xilinx IP cores. Use when instantiating IP catalog cores, configuring AXI interconnects, generating IP targets, handling OOC synthesis, upgrading stale IPs, or building block designs.
metadata	{"openclaw":{"requires":{"bins":["vivado"]},"emoji":"📦"}}

Vivado IP Runbook

1. IP Creation & Config

create_ip -name <core_name> -vendor xilinx.com -library ip -module_name <inst_name>
set_property CONFIG.PARAM_NAME <value> [get_ips <inst_name>]
generate_target all [get_ips <inst_name>]

2. IP Status Audit

foreach ip [get_ips] {
  set status [get_property IP_INTEGRATION_STATUS $ip]
  set locked [get_property IS_LOCKED $ip]
  puts "IP: $ip | Status: $status | Locked: $locked"
}

3. Upgrade Flow

report_ip_status -file /tmp/vivaclaw_rpt/ip_status.rpt
upgrade_ip [get_ips -filter {UPGRADE_AVAILABLE == 1}]

4. Block Design (BD) Basics

create_bd_design "system"
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_intercon
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/cpu/M_AXI" }  [get_bd_intf_pins axi_intercon/S00_AXI]
validate_bd_design
save_bd_design

5. License Check

get_property IS_EVALUATION [get_ips <inst_name>]

Warning: Evaluation IPs produce bitstreams that expire after a few hours of hardware operation.