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Run native KiCad DRC with smart violation filtering, delta tracking, and fix suggestions
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Basierend auf der SOC-Berufsklassifikation
Full PCB verification loop using local kicad-cli (DRC + 3D render + gerbers)
Create a new Claude Code skill for this project. Use when you need to add a new skill, improve an existing skill, or convert a workflow into a reusable skill.
Verifies that every PCB pad-to-net assignment matches the manufacturer datasheet pin specifications. Use when changing board.py/routing.py/footprints.py, after GPIO remapping, before releases, or when adding new components. Automated guard against wiring errors like unconnected VBUS, wrong pin assignments, or missing GND connections.
Design intent adversary — cross-checks GPIO, nets, power chains, signal paths across firmware/schematic/PCB/datasheet sources to find lost connections and inconsistencies
Analyze a DFM report and fix all issues in the PCB generation scripts
Run DFM guard tests and add new regression tests after fixing PCB issues
| name | drc-native |
| model | claude-opus-4-7 |
| description | Run native KiCad DRC with smart violation filtering, delta tracking, and fix suggestions |
| disable-model-invocation | true |
| allowed-tools | Bash, Read, Grep, Glob, Edit, Write |
Run kicad-cli DRC and analyze violations with smart filtering, delta tracking, and fix suggestions.
cd /Users/pierrejonnycau/Documents/WORKS/esp32-emu-turbo
kicad-cli pcb drc \
--output /tmp/drc-report.json \
--format json \
--severity-all \
--units mm \
--all-track-errors \
hardware/kicad/esp32-emu-turbo.kicad_pcb
python3 scripts/drc_native.py /tmp/drc-report.json
The script categorizes violations into:
For each real issue, the script maps it to the source file that controls it:
| Violation Type | Source File | Suggested Fix |
|---|---|---|
clearance | scripts/generate_pcb/routing.py | Increase trace spacing or move traces apart |
copper_edge_clearance | scripts/generate_pcb/routing.py | Move traces away from board edge or FPC slot |
silk_over_copper | scripts/generate_pcb/board.py | Move silkscreen text to Fab layer |
silk_overlap | scripts/generate_pcb/board.py | Reduce text size or reposition labels |
silk_edge_clearance | scripts/generate_pcb/board.py | Move silkscreen text away from board edge |
track_width | scripts/generate_pcb/routing.py | Increase trace width constants |
via_annular_ring | scripts/generate_pcb/primitives.py | Increase via size or reduce drill diameter |
unconnected_items | scripts/generate_pcb/routing.py | Add missing trace connection |
min_copper_clearance | scripts/generate_pcb/routing.py | Increase clearance between copper elements |
After fixing issues or accepting the current state, save a new baseline:
python3 scripts/drc_native.py /tmp/drc-report.json --update-baseline
/verify: Uses custom Python DRC checks (15 tests)/check: Full pipeline (generate -> DRC -> render -> gerbers)/drc-native: Focused DRC-only with smart filtering, delta tracking, and fix mappingscripts/drc_native.py -- Smart DRC analysis wrapperscripts/drc_baseline.json -- Violation baseline (auto-generated)hardware/kicad/esp32-emu-turbo.kicad_pcb -- PCB file to check