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Run the full PCB generation pipeline (generate + zone fill + gerbers + release package)
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Basierend auf der SOC-Berufsklassifikation
| name | generate |
| model | claude-opus-4-7 |
| description | Run the full PCB generation pipeline (generate + zone fill + gerbers + release package) |
| disable-model-invocation | true |
| allowed-tools | Bash, Read, Grep, Glob |
Run the complete ESP32-emu-turbo PCB generation pipeline end-to-end.
cd /Users/pierrejonnycau/Documents/WORKS/esp32-emu-turbo
python3 -m scripts.generate_pcb hardware/kicad
This generates:
hardware/kicad/esp32-emu-turbo.kicad_pcb (PCB layout)hardware/kicad/jlcpcb/bom.csv (Bill of Materials)hardware/kicad/jlcpcb/cpl.csv (Component Placement List)docker compose run --rm --entrypoint python3 kicad-pcb /scripts/kicad_fill_zones.py "/project/esp32-emu-turbo.kicad_pcb"
This fills copper zones (In1.Cu=GND plane, In2.Cu=3V3/5V planes) and preserves orphan nets (USB_CC1/CC2).
docker compose run --rm kicad-pcb pcb export gerbers \
--output /gerbers/ \
--layers "F.Cu,In1.Cu,In2.Cu,B.Cu,F.Paste,B.Paste,F.SilkS,B.SilkS,F.Mask,B.Mask,Edge.Cuts" \
--subtract-soldermask --use-drill-file-origin \
"/project/esp32-emu-turbo.kicad_pcb"
docker compose run --rm kicad-pcb pcb export drill \
--output /gerbers/ --format excellon --drill-origin plot \
--excellon-units mm --generate-map --map-format gerberx2 \
"/project/esp32-emu-turbo.kicad_pcb"
cd hardware/kicad/gerbers
zip -j ../jlcpcb/gerbers.zip *.gtl *.g1 *.g2 *.gbl *.gto *.gbo *.gts *.gbs *.gtp *.gbp *.gm1 *.drl *.gbrjob 2>/dev/null
cp hardware/kicad/jlcpcb/bom.csv release_jlcpcb/bom.csv
cp hardware/kicad/jlcpcb/cpl.csv release_jlcpcb/cpl.csv
rm -rf release_jlcpcb/gerbers
cp -r hardware/kicad/gerbers release_jlcpcb/gerbers
cp hardware/kicad/jlcpcb/gerbers.zip release_jlcpcb/gerbers.zip
After the pipeline completes, run DFM + DFA verification:
python3 scripts/verify_dfm_v2.py
python3 scripts/verify_dfa.py
Report results as a summary table (43 DFM + 9 DFA tests).
/Users/pierrejonnycau/Documents/WORKS/esp32-emu-turbodocker compose buildscripts/generate_pcb/__init__.py → calls generate_board() + export_cpl()scripts/generate_pcb/board.pyscripts/generate_pcb/routing.pyscripts/generate_pcb/footprints.pyscripts/generate_pcb/jlcpcb_export.pyscripts/kicad_fill_zones.pyscripts/export-gerbers-fast.shscripts/export-gerbers.shscripts/verify_dfa.pyFull PCB verification loop using local kicad-cli (DRC + 3D render + gerbers)
Create a new Claude Code skill for this project. Use when you need to add a new skill, improve an existing skill, or convert a workflow into a reusable skill.
Verifies that every PCB pad-to-net assignment matches the manufacturer datasheet pin specifications. Use when changing board.py/routing.py/footprints.py, after GPIO remapping, before releases, or when adding new components. Automated guard against wiring errors like unconnected VBUS, wrong pin assignments, or missing GND connections.
Design intent adversary — cross-checks GPIO, nets, power chains, signal paths across firmware/schematic/PCB/datasheet sources to find lost connections and inconsistencies
Analyze a DFM report and fix all issues in the PCB generation scripts
Run DFM guard tests and add new regression tests after fixing PCB issues