DV-Skills

DEMO/TEMPLATE domain sub-skill for PCIe subsystem RTL debug. Plugs into the parent rtl-sim-debug skill. Triggers on PCIe LTSSM, TLP, DLLP, flow control, PIPE, controller/PHY messages. Scope covers PCIe controller, PIPE PHY, link training, TLP layer. Not a real PCIe debug skill — built to teach how to author rtl-sim-debug-<subsystem> skills. Rename/flesh out to productize.

Debug failing or hung VCS+UVM RTL simulations. Triggers on UVM_ERROR, UVM_FATAL, sim hang, testcase failure, waveform debug, assertion failure, X-propagation, .vcd/.fsdb inspection, or any request to root-cause an RTL simulation issue. Orchestrates log triage, classification (TB vs RTL vs config vs env), JIRA + regression-history correlation, waveform-driven driver tracing across large RTL hierarchies, and produces a JIRA-ready writeup (RTL bugs) or a concrete edit (TB/config bugs). Agent-agnostic — works on any skill-aware runtime. Auto-dispatches to domain sub-skills named rtl-sim-debug-<subsystem> when matching triggers are present.

Analyses VCS urg coverage reports (code + functional), identifies gaps, suggests test stubs or exclusions, generates .el exclusion files, evaluates per-milestone closure criteria, and produces a combined sign-off HTML report integrating S7 (assertions), S9 (regression), and S10 (coverage) data.

Design Verification skill (S9) that generates a complete regression infrastructure: milestone test lists, parallel regression runner with grid support, VCS log parser, HTML regression report, and VCS/Verdi coverage merge. Reads test inventory from S6 dv_sequences_data.json and build/sim commands from S4/S5. Use this skill whenever a user wants to: - Generate DV regression test lists (DV-I / DV-C / DV-F) - Run regression with keyword-based test selection - Set up parallel regression on a compute grid (LSF/SGE/Slurm/custom) - Generate an HTML regression report with CHK_ID failure details - Merge VCS coverage databases and generate coverage report - Run /dv-regression or S9 in the DV end-to-end flow Trigger on: "run regression", "generate testlist", "dv-regression", "/dv-regression", "S9", "regression runner", "run all tests", "coverage merge", "regression report", "failing tests"

Design Verification skill (S8) that generates a complete scoreboard and reference model implementation for a UVM testbench. Builds on top of the S5 skeletons, implements per-feature check tasks, CHK_ID-mapped pass/fail reporting, reference model with analysis port to scoreboard, and a functional coverage model that receives passing transactions from the scoreboard via analysis port. This skill is HIGHLY INTERACTIVE — it asks the user targeted questions after analyzing the design, testplan, and existing checker coverage before generating any code. Use this skill whenever a user wants to: - Implement the DV scoreboard for a UVM testbench - Implement a reference / prediction model - Generate functional coverage model fed from scoreboard pass events - Generate CHK_ID-mapped check tasks from testplan - Run /dv-scoreboard or S8 in the DV end-to-end flow Trigger on: "generate scoreboard", "implement scoreboard", "dv-scoreboard", "/dv-scoreboard", "S8", "reference model", "implement checker", "scoreboard implement

Design Verification skill (S7) that generates SystemVerilog Assertions (SVA) for every protocol interface and DUT-internal signal in the verification environment. Consumes testplan assertion_code (S2), TB data (S5), and sequences data (S6). Generates per-VIP assertion modules, a DUT bind module for internal assertions, assertion control package, UVM assertion reporter, and a top-level assertions package. Use this skill whenever a user wants to: - Generate SVA files from a DV testplan (S2 Excel or JSON) - Create per-VIP interface assertion modules with assert+cover properties - Create a DUT bind module for internal/hierarchical assertions - Generate assertion control (enable/disable per group or phase) - Generate a UVM assertion checker that reports CHK_ID pass/fail at sim end - Run /dv-assertions or S7 in the DV end-to-end flow Trigger on: "generate assertions", "generate SVA", "dv-assertions", "/dv-assertions", "S7", "write SVA", "create property", "bind assertions", "assertion report", "cover property", "

Design Verification skill that generates a complete, synthesizable UVM testbench scaffold for a hardware DUT. Identifies all unique VIP protocols from the DUT interface list, generates fully parameterized UVM VIP components for each (driver, monitor, sequencer, sequence item, config, agent, functional coverage, base sequences, interface with clocking blocks/modports/SVA), generates a UVM RAL model from the register map, generates the top-level UVM environment (env, env_cfg, scoreboard, reference model, virtual sequencer), and produces a DUT RTL stub for immediate compilation. All generated code is complete, syntactically correct SystemVerilog/UVM that compiles with VCS. Use this skill whenever a user wants to: - Generate a UVM testbench scaffold from a DUT spec or S1/S2/S3/S4 outputs - Create VIP (agent/driver/monitor/sequencer/coverage) for AXI/AHB/APB/SPI/I2C/UART or any proprietary protocol - Generate a UVM RAL model from a register map - Create a DUT RTL stub for testbench bring-up - Set up the full UV

Design Verification skill (S6) that generates UVM sequences, virtual sequences, and UVM test classes from a DV testplan (Excel or JSON) and an existing UVM testbench (described by dv_tb_data.json from S5, or by scanning the dv/ tree). Use this skill whenever a user wants to: - Generate UVM sequences and tests from a DV testplan (S2 Excel or JSON) - Create directed test sequences for specific testplan rows - Create randomized virtual sequences for coverage-driven tests - Generate per-VIP protocol sequences (write, read, burst, error injection) - Generate UVM test classes with plusargs, cfg constraints, and vseq execution - Generate a single testcase interactively from a natural-language description - Run /dv-sequences or S6 in the DV end-to-end flow Trigger on: "generate sequences", "generate tests", "dv-sequences", "/dv-sequences", "create testcases", "write sequence for", "S6", "generate test from testplan", "create directed test", "create random test", "generate vseq", "write a test that"

Design Verification skill that generates a comprehensive, structured testplan Excel workbook (testplan.xlsx) from a hardware design spec. Accepts either a dv_spec_summary.json (output of dv-spec-parse / S1) or a raw spec file (PDF/DOCX/TXT/MD) directly. Use this skill whenever a user wants to: - Generate a DV testplan from a design spec or parsed spec JSON - Create a structured Excel testplan with features, testcases, coverage, checkers - Map design features to verification types (directed test, random test, coverpoint, checker) - Generate SystemVerilog covergroup/coverpoint code for functional coverage - Define checker IDs and types for a DV project - Plan milestone-tagged tests (DV-I, DV-C, DV-F) - Run /dv-testplan or S2 in the DV end-to-end flow Trigger on: "generate testplan", "create testplan", "dv-testplan", "/dv-testplan", "testplan from spec", "write testplan", "S2", "map features to tests", "create coverage plan", "define checkers for", "testplan excel"

Generates a complete, professional DV Verification Plan PDF document for a hardware IP block. Use this skill whenever the user wants to create a verification plan, DV plan, VP document, or signoff plan for a hardware block or IP. Triggers on: "create verification plan", "generate DV plan", "write verif plan", "create VP document", "DV planning document", "signoff plan", or any request to document the verification strategy for an IP/DUT. Accepts S1 spec summary JSON and/or S2 testplan Excel as inputs, or a raw spec file. Produces a polished PDF with embedded PNG block diagrams (TB architecture, DUT diagram, Gantt schedule), interactive Q&A for all sections, and a machine-readable JSON for downstream DV skills (S4 onward). Always use this skill for verif plan creation — do NOT attempt to generate a verification plan without it.

Design Verification skill that parses a hardware design specification document (PDF, DOCX, TXT, or Markdown) and extracts all structured information needed to kick off a DV project — features, interfaces, signals, parameters, clocks, resets, operating modes, and compliance standards. Use this skill whenever a user wants to: - Start a DV project from a spec or design document - Extract features, interfaces, or signals from a hardware spec - Generate a structured DV spec summary from a PDF, Word doc, or text file - Prepare inputs for testplan generation (S2/dv-testplan) - Parse or analyse a design spec for verification planning purposes Trigger on phrases like: "parse my spec", "read the design doc", "extract features from spec", "start DV from this spec", "analyse this design document", "what are the interfaces in this spec", "generate spec summary", "dv-spec-parse", "/dv-spec-parse"

Design Verification skill that sets up the complete DV project environment for a hardware verification project. Generates directory scaffold, VCS Makefile with all switches, compilation flow, UVM testbench skeleton files, environment scripts, and synopsys_sim.setup. Output dv_env_data.json feeds downstream TB scaffold (S5). Use this skill whenever a user wants to: - Set up a new DV project directory and simulation environment - Generate a VCS Makefile with wave/coverage/log/plusarg switches - Create UVM testbench skeleton files (env, scoreboard, coverage, sequences, tests) - Generate proj.cshrc / proj.bashrc / .env environment setup scripts - Create synopsys_sim.setup, compile.f, regression.sh for VCS - Initialize the DV directory structure for a new IP or block - Run /dv-env-setup or S4 in the DV end-to-end flow Trigger on: "setup DV environment", "create DV project", "generate Makefile", "dv-env-setup", "/dv-env-setup", "S4", "set up simulation", "VCS Makefile", "create TB skeleton", "setup UVM environmen