yamato720

维护 `npc/VerilogVisualization` 的 RTL 发现、已保存设计 JSON、数据流可视化布局、刷新保留状态和同步控制。处理 Verilog/SystemVerilog 分析结果、`data/VerilogVisualization/*.json`、模块位置冲突、手工 JSON 布局被浏览器缓存覆盖，或需要按硬件数据流重排可视化设计图时使用。

Operate the YSYX workbench's Config-driven NPC, ysyxSoC, NEMU-host, and FPGA construction workflow. Use when inspecting or changing Scala CDE Config composition, `make config=`, construction versions, `run`/`run-bat`, NEMU host builds, FPGA board settings, generated RTL routing, or NPC/SoC memory integration in this repository.

Use when working in the Project-XPlus / Project-X / Project-XS codebase, especially Cuper, TAPA, U55C, Vitis/Vivado, bitstream generation, tmux hardware builds, 395bitstream synchronization, demo bitstream testing, docs/bitstream_summaries version records, source.diff, testing.md, or code_reading_guide.md.