analog-circuit-skills

Two-stage CMOS operational amplifier simulation skill. Use when the user wants to simulate or size a Miller-compensated two-stage op amp with PMOS differential input pair, NMOS current-mirror first-stage load, NMOS common-source second stage, PMOS current-source load, bias mirror, Cc compensation, and CL load. Supports ngspice DC operating point, AC gain/phase sweep, pole-zero analysis, and output-noise analysis.

Five-transistor OTA simulation and analysis skill. Use when the user wants to simulate or size a classic 5T CMOS OTA: NMOS differential input pair, PMOS current-mirror active load, and NMOS tail current transistor. Supports ngspice DC transfer, AC gain/bandwidth/phase, output-noise analysis, and first-order design interpretation. Requires ngspice on PATH and Python 3 with numpy/matplotlib/scipy.

PTM 180nm PMOS-pass LDO regulator simulation, sizing, and analysis skill. Use this skill whenever the user wants to: (1) simulate or re-run LDO DC/AC/noise/transient analyses in ngspice, (2) plot loop gain, PSRR, output impedance, load-step response, noise PSD, or transistor operating points, (3) compute or verify initial transistor sizing from specs (Vin, Vout, Iload, Cload, Vref), (4) iteratively adjust device sizes to meet specs (output accuracy ±1%, phase margin, PSRR, load/line regulation, noise, offset), (5) apply theoretical formulas for GBW, zero/pole frequencies, PSRR, load regulation, noise, or offset, (6) perform trade-off analysis between competing specs, (7) learn LDO topology, compensation theory, or sizing methodology. Technology: PTM 180nm BSIM3v3 (NMOS/PMOS, Lmin=180nm, Wmin=220nm, VDD up to 3.3V). Requires: ngspice on PATH, Python 3 + numpy/matplotlib/scipy.

Bootstrapped sampling switch simulation and analysis skill for SAR ADC design. Use when the user wants to: (1) simulate a bootstrap switch with ngspice (180nm PTM, VDD=1.8V), (2) verify the bootstrap mechanism — gate voltage tracks Vin+VDD, (3) compare on-resistance (Ron) of NMOS vs CMOS vs bootstrap switch across input range, (4) study clock feedthrough and charge injection effects, (5) understand the bootstrap switch circuit topology, working phases, or transistor roles, (6) size transistors for a bootstrap switch (sampling switch W, bootstrap capacitor CB). Requires: ngspice skill installed, Python 3 with numpy/matplotlib.

StrongArm dynamic comparator simulation and analysis skill. Use this skill whenever the user wants to simulate, analyse, or learn about a StrongArm (or similar dynamic) comparator. Trigger on any of: (1) run a comparator transient simulation in ngspice, (2) plot waveforms of internal nodes (VXP/VXN, VLP/VLN, OUTP/OUTN), (3) measure or sweep comparison time Tcmp, latch time constant τ, average power, energy per cycle, or FOM, (4) extract input-referred noise sigma via noise counting / probit / Gaussian CDF fit, (5) sweep transistor widths (tail, input pair, latch NMOS/PMOS) to study speed–power–noise trade-offs, (6) simulate offset voltage with ramp or binary-search method, (7) learn the StrongArm topology, four operating phases, noise/offset/speed theory, or transistor sizing guidance. Requires: ngspice on PATH, Python 3 + numpy/matplotlib/scipy.