memory-bus-architecture

name	memory-bus-architecture
description	This skill should be used when the user asks about "bus architecture", "AHB APB buses", "bus matrix", "DMA channels", "clock tree", "S-Bus", "I-Bus", "D-Bus", "memory organization", "clock configuration", "PLL setup", "RCC", or needs to understand STM32 internal bus structure, DMA-to-peripheral mapping, or clock domain relationships from the reference manual.
version	1.0.0

Memory and Bus Architecture Extraction

Extract and interpret STM32 bus architecture, memory organization, and clock tree configuration from user-provided reference manual PDFs.

What to Extract

Bus Architecture

• Bus matrix connections (which masters connect to which slaves)
• AHB buses: AHB1, AHB2, AHB3 (and which peripherals are on each)
• APB buses: APB1 (low-speed), APB2 (high-speed) and their max frequencies
• Cortex-M buses: I-Bus (instruction), D-Bus (data), S-Bus (system)
• Bus arbitration: round-robin vs fixed priority

DMA Architecture

• DMA controller count (DMA1, DMA2)
• Streams/channels per controller
• DMA request mapping: which peripheral is on which stream/channel
• DMA bus connections: which DMA can access which memory/peripheral
• FIFO configuration options

Clock Tree

• Clock sources: HSI, HSE, LSI, LSE, MSI (if applicable)
• PLL configuration: input source, multiplication/division factors
• SYSCLK source selection
• AHB prescaler (HCLK)
• APB1 prescaler (PCLK1) and APB2 prescaler (PCLK2)
• Peripheral clock sources and maximum frequencies
• MCO (Microcontroller Clock Output) options

Where to Find This Information

Reference Manual - Bus Architecture

Glob pattern: docs/reference-manual/*.pdf

1. Read pages 1-5 (table of contents)
2. Find chapter titled "System and memory overview" or "Memory and bus architecture" (typically chapter 2)
3. Read that chapter (usually 10-20 pages) to find:
   • System architecture block diagram (bus matrix figure)
   • Bus matrix table showing master/slave connections
   • Memory map table with address ranges
4. Find chapter titled "DMA controller" or "DMA"
   • DMA request mapping table (critical: shows which peripheral maps to which stream/channel)
   • DMA block diagram showing bus connections

Reference Manual - Clock Tree

1. From ToC, find chapter titled "Reset and clock control (RCC)"
2. Read the clock tree figure (usually one of the first figures in the RCC chapter)
3. Extract PLL configuration registers and prescaler options
4. Find the table showing maximum frequencies per bus domain

Extraction Process

1. Glob docs/reference-manual/*.pdf
2. Read pages 1-5 (ToC) to locate chapter numbers
3. Read the "System and memory overview" chapter to extract bus matrix
4. Read the "DMA" chapter to extract DMA request mapping table
5. Read the "RCC" chapter to extract clock tree configuration
6. Compile into structured output

Key Concepts to Document

Bus Matrix Interpretation

The bus matrix is a crossbar switch. Masters (CPU, DMA, Ethernet, USB) on rows, slaves (Flash, SRAM, peripherals) on columns. A connection means the master can access the slave. Multiple masters can access different slaves simultaneously, but conflicts on the same slave cause arbitration delays.

DMA Channel Selection

This is critical for code generation. Each peripheral's DMA request is hardwired to specific streams/channels. Two peripherals sharing the same stream cannot use DMA simultaneously. Extract the complete mapping table.

Clock Domain Boundaries

Peripherals on APB1 run at a lower frequency than APB2. When configuring baud rates or timer prescalers, use the correct bus clock (PCLK1 or PCLK2), not SYSCLK. Timer clocks may be 2x their APB clock if the APB prescaler is not 1.

Output Format

## Bus Architecture

**Bus Matrix Masters**: Cortex-M4 (I-Bus, D-Bus, S-Bus), DMA1, DMA2, Ethernet, USB OTG HS
**Bus Matrix Slaves**: Flash, SRAM1, SRAM2, AHB1, AHB2, APB1, APB2

**AHB1 Peripherals**: GPIOA-K, CRC, DMA1, DMA2, Ethernet MAC, USB OTG HS
**AHB2 Peripherals**: USB OTG FS, DCMI, RNG, HASH, CRYP
**APB1 Peripherals** (max 42 MHz): TIM2-7, TIM12-14, USART2-5, UART7-8, SPI2-3, I2C1-3, CAN1-2, DAC, PWR
**APB2 Peripherals** (max 84 MHz): TIM1, TIM8-11, USART1, USART6, SPI1, SPI4-6, ADC1-3, SDIO, SYSCFG

## DMA Request Mapping
[Table of DMA stream -> peripheral request mappings]

## Clock Tree
**HSE**: [frequency from user manual/schematic]
**PLL**: HSE/M * N / P = SYSCLK
**HCLK**: SYSCLK / AHB_prescaler
**PCLK1**: HCLK / APB1_prescaler (max XX MHz)
**PCLK2**: HCLK / APB2_prescaler (max XX MHz)

Additional Resources

Reference Files

• references/bus-architecture-guide.md - Patterns for interpreting bus matrix diagrams across STM32 families, DMA request table formats, clock tree calculation methods