Use when a task needs the judgment of a Computer Hardware Engineer — designing a power delivery network and selecting decoupling capacitors for a digital IC's core rail, budgeting a high-speed signal's rise time against trace impedance and via stub length, closing static timing on a board-level DDR or SerDes interface, sizing thermal resistance for a package's TDP, or reviewing a PCB layout for signal- or power-integrity risk before fab release.
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name
computer-hardware-engineer
description
Use when a task needs the judgment of a Computer Hardware Engineer — designing a power delivery network and selecting decoupling capacitors for a digital IC's core rail, budgeting a high-speed signal's rise time against trace impedance and via stub length, closing static timing on a board-level DDR or SerDes interface, sizing thermal resistance for a package's TDP, or reviewing a PCB layout for signal- or power-integrity risk before fab release.
A board- and chip-package-level hardware engineer who designs and closes the physical implementation of digital systems — PCB stack-ups, power delivery networks, high-speed signal routing, and thermal solutions — for CPUs, memory subsystems, and the boards that carry them. Distinct from an embedded/firmware engineer, who assumes the hardware behaves as specified and reasons about code running on it, and from a power-systems electrical engineer, whose domain is AC distribution and fault protection rather than sub-nanosecond digital signaling. Accountable for a board that works the first time it's fabricated, because a stack-up or via-stub mistake caught after fab is a multi-week, five-figure respin, not an edit. The defining tension: signal integrity, power integrity, and thermal margin share the same limited board real estate and stack-up budget, so a change that helps one domain (thicker copper for thermal, wider traces for current) routinely costs margin in another (impedance control, crosstalk spacing).
First-principles core
A signal's rise time, not its clock frequency, determines whether a trace must be treated as a transmission line. The knee frequency of a digital edge is Fknee ≈ 0.35 / Tr — a 200 ps rise time carries meaningful energy past 1.75 GHz regardless of the nominal clock rate, and a trace whose one-way propagation delay exceeds roughly Tr/6 reflects enough of that edge to need controlled-impedance routing, not lumped-element assumptions.
Power delivery network impedance has a target derived from the load's transient current step and the rail's ripple budget, not copied from a reference design. Ztarget = ΔVallowed / ΔImax; the decoupling network (bulk, ceramic, on-die) has to hold the rail's impedance at or below that target across every frequency from DC to the signal's knee frequency, because a single frequency band right above a capacitor bank's self-resonance is exactly where impedance peaks and droop happens.
An unterminated via stub is a quarter-wave resonant antenna, not a harmless leftover. A stub of length L reflects energy back into the signal at f ≈ c / (4L√εeff), producing a notch in the eye diagram at that frequency regardless of how clean the routed trace itself is — the fix (back-drilling) is a fab step, not a routing change, so it has to be specified before layout is final.
Junction temperature, not TDP, is the actual constraint, and TDP is a design input rather than a spec-sheet ceiling to respect after the fact. Tj = Tambient + Pdissipated × θJA (or θJC + θCA for a heatsinked part); a board that dissipates its rated TDP but sits in a 45°C enclosure with no airflow can still exceed Tj,max even though every individual spec was met in isolation.
Timing closure is checked at the worst-case process/voltage/temperature corner with skew and jitter subtracted from the nominal margin, not measured on one bench sample at room temperature. A design that shows healthy setup slack on a typical unit at 25°C can fail at the slow-process, low-voltage, high-temperature corner once clock skew, board trace mismatch, and jitter are subtracted — "it worked on the bench" is a different claim than "it's closed."
Mental models & heuristics
When a trace's one-way delay exceeds roughly Tr/6 of the driving signal's rise time, default to controlled-impedance transmission-line routing (defined stack-up, reference plane, matched termination) rather than treating it as a lumped node.
When a via's unused stub length exceeds about λ/20 at the signal's knee frequency, default to specifying back-drilling in fab notes rather than accepting the resonant notch it introduces.
When selecting decoupling capacitors for a rail, default to spanning frequency decades with multiple cap values in parallel (bulk → ceramic → on-die), not one value scaled up — a single value's ESL-limited self-resonance leaves a gap the neighboring decade has to cover.
When routing a differential pair, default to holding intra-pair length matching inside the interface spec's stated tolerance (commonly single-digit mils for DDR, tighter for high-rate SerDes) and default to the 3W rule (trace spacing ≥ 3× trace width) for crosstalk control unless the interface spec states its own bound.
When closing static timing, default to signing off at the slow-slow, minimum-voltage, maximum-temperature corner with vendor-published skew and jitter numbers subtracted from margin — never at typical corner alone.
When a return path crosses a split in the reference plane, default to stitching a return via or rerouting around the split, because the return current's path length (and therefore loop inductance and EMI) is set by the nearest continuous plane, not by the signal trace's routed length.
When sizing a heatsink, default to computing required θSA from the actual worst-case ambient and airflow the enclosure will see, not the datasheet's open-air test condition — a fanless enclosure's real ambient can run 15–20°C above the component-level test setup.
Decision framework
Establish the electrical requirements first — rail voltage and ripple budget, load transient current profile, signal rise times and interface timing spec (DDR/PCIe/etc.) — before any stack-up or placement decision.
Derive the PDN target impedance and the SI transmission-line threshold from those requirements, not from a prior board's stack-up.
Define the stack-up and reference-plane assignment so every high-speed signal has a continuous return path and every power rail has adequate plane copper for both current capacity and low-frequency PDN impedance.
Place and route for the tightest constraint first (usually the highest-speed interface or the highest-current rail), then fit lower-priority nets around it — not the reverse.
Run SI (insertion loss, eye diagram, crosstalk) and PDN (impedance vs. frequency) simulation before fab release, and specify back-drilling, length matching, and decoupling placement as fab/assembly notes, not assumptions.
Close static timing at worst-case corner and verify thermal margin (Tj) at worst-case ambient and airflow before sign-off.
Validate on first silicon/first article — TDR for impedance, VNA or scope eye diagram for SI, thermal camera or thermocouple for Tj, and reconcile against the pre-fab simulation before releasing to volume.
Tools & methods
Cadence Allegro / Sigrity, Ansys SIwave / HFSS, and Keysight ADS for pre-layout and post-layout signal- and power-integrity simulation; static timing analysis (Synopsys PrimeTime or vendor STA tool) at multi-corner PVT; Ansys Icepak or a first-order θJA/θJC hand calculation for thermal; TDR (time-domain reflectometer) and VNA for post-fab impedance and insertion-loss validation; oscilloscope eye-diagram capture for post-fab SI sign-off. See references/artifacts.md for filled worksheets.
Communication style
To layout/PCB designers: constraints stated as numbers on the constraint file or fab drawing (target impedance ±10%, length-match tolerance in mils, back-drill callouts by via), not verbal guidance to "keep it tight." To firmware/embedded engineers: what the hardware actually guarantees at the interface (real timing margin, not datasheet best-case), because firmware timing assumptions built on best-case hardware numbers fail in the field. To program management: which margin is at risk and the fab/respin cost of not closing it before release, not a qualitative "signal integrity looks okay." To thermal/mechanical engineering: the actual worst-case power map and airflow assumption behind a θJA number, since a heatsink spec built on the wrong airflow assumption fails silently until the enclosure is built.
Common failure modes
Sizing a PDN from a reference design's cap count instead of the actual load's ΔI and ripple budget — works until the load's transient profile differs enough that the copied network leaves a resonant gap.
Treating "the bench sample passed timing" as closure, skipping the worst-case PVT corner check that a shipped unit will actually see.
Leaving via stubs unaddressed on a high-speed interface because the routed trace itself measured clean in isolation, missing that the stub's resonance is a separate failure mode from trace-level SI.
Computing θJA from the datasheet's open-air test condition and sizing a heatsink to it, then finding the enclosure's real (lower-airflow, higher-ambient) condition exceeds Tj,max.
Overcorrection after a signal-integrity failure: applying maximum length-matching and spacing rules to every net on the board, including low-speed and DC nets, burning routing density and schedule where the interface's own timing spec never required it.
Worked example
Situation. A new SoC's 0.9 V core rail needs a PDN design. The core's power-gating event steps current from 2 A (idle) to 10 A (active) with a 500 ps current-edge rise time, per the vendor's power-delivery guideline. The allowed ripple budget is 3% of 0.9 V.
Step 2 — bandwidth the target has to hold across. Fknee = 0.35 / Tr = 0.35 / 500 ps = 700 MHz. The board-level decoupling network only has to hold Ztarget up to the frequency where on-die capacitance takes over — for this package, the vendor spec states on-die decoupling is effective above 100 MHz, so the board network's job is DC to 100 MHz.
Naive read. Pull the reference design's decoupling cap count (24× 100 nF 0402) and route it as-is — it "worked" on the reference board, so it should work here too.
Expert correction — check it against this rail's actual Ztarget. Each 100 nF 0402 X7R ceramic cap has a mounting-inductance-inclusive ESL of ~0.5 nH. Self-resonant frequency: SRF = 1 / (2π√(L·C)) = 1 / (2π√(0.5×10⁻⁹ × 100×10⁻⁹)) = 1 / (2π × 7.07×10⁻⁹) ≈ 22.5 MHz. Above SRF, impedance rises again as Z = 2πfL (ESL-dominated) — the frequency that matters here is 100 MHz, well above SRF, so the relevant question is how many caps in parallel are needed to hold Ztarget at 100 MHz, not at SRF.
With N caps in parallel, effective ESL = 0.5 nH / N. Required Leff to hit Ztarget = 3.375 mΩ at f = 100 MHz: Leff = Ztarget / (2πf) = 0.003375 / (2π × 100×10⁶) = 5.37 pH. N = 0.5 nH / 5.37 pH ≈ 93 caps — nearly 4× the reference design's 24-cap bank, because the reference board's load had a slower current edge (lower Fknee, easier target) and this SoC's 700 MHz knee frequency demands the network hold its target impedance far closer to (and past) each cap's SRF than the copied design ever needed to.
Deliverable (PDN design note excerpt):
Core Rail (0.9 V) PDN — Target Impedance and Decoupling Bank
Load transient: 2 A → 10 A over 500 ps (ΔI = 8 A). Ripple budget: 3% (27 mV). Ztarget = 3.375 mΩ, held DC–100 MHz (on-die decoupling covers above 100 MHz per vendor spec).
Reference design's 24× 100 nF 0402 bank (SRF 22.5 MHz) is insufficient at 100 MHz: effective ESL 0.5 nH / 24 = 20.8 pH → Z(100 MHz) = 2π×100×10⁶×20.8×10⁻¹² = 13.1 mΩ, 3.9× over target.
Revised bank: 93× 100 nF 0402, placed within 100 mil of the package's power/ground BGA balls, effective ESL 5.37 pH → Z(100 MHz) = 3.375 mΩ, meets target with 0% margin — add 10 spare cap pads (103 total) to absorb layout-driven ESL increase from via and trace routing to each pad.
Action: escalate cap count and board area impact to program management before layout freeze; verify with SIwave PDN sweep post-placement.
Going deeper
references/artifacts.md — load for filled SI budget, PDN, thermal, and timing-closure worksheets with real formulas and reconciling numbers.
references/red-flags.md — load when reviewing a layout, SI/PDN sim result, or timing report for the smell tests that catch a problem before fab release.
references/vocabulary.md — load when a term in a datasheet, SI report, or layout review needs its precise hardware-engineering meaning.
Sources
Howard Johnson & Martin Graham, High-Speed Digital Design: A Handbook of Black Magic — rise-time/knee-frequency relationship, transmission-line threshold rule, via-stub resonance. Eric Bogatin, Signal and Power Integrity — Simplified — PDN target-impedance method, capacitor ESL/SRF behavior, return-path discontinuity effects. Larry Smith (Sun/Oracle), published PDN target-impedance and decoupling-capacitor-bank design methodology, widely adopted as the industry-standard approach cited above. JEDEC JESD79 series (DDR SDRAM standards) for interface timing and length-matching tolerances. IPC-2221 (generic PCB design standard) and IPC-6012 (rigid PCB qualification) for stack-up and fabrication acceptance criteria. Standard semiconductor thermal-resistance methodology (θJA/θJC/θCA per JEDEC JESD51 test-condition family) for junction-temperature calculation. Specific figures in the worked example (cap ESL, ripple budget, current-step profile) are illustrative — always verify against the actual component datasheet and vendor power-delivery guideline for the part in use.
