This skill should be used when initializing a new RTL project with directory structure, rules, guides, and template files. Triggers on 'init project', 'initialize project', 'new project', 'project init'.
SystemVerilog coding convention and design guideline skill. Enforces lowRISC style + project overrides for all .sv/.v file generation. Covers naming, module structure, power optimization, FPGA considerations, and pipelining for timing closure.
Passive synthesis tool profiles (yosys, dc_shell, genus) for replayable runs and comparable summary outputs.
Policy rules, weights defaults, timing-first heuristic, convergence criteria, DC Tcl fragments, and rollback protocol for the DC-based PPA optimization pipeline. Pure reference — no orchestration.
This skill should be used when the user asks to "develop BFM", "create SystemC TLM model", "build bus functional model", "implement TLM-2.0 BFM", "model AMBA protocol in SystemC", or when Phase 3 transaction-level models are needed for performance estimation or protocol verification.
This skill should be used when the user asks to "build a reference model", "create C ref model", "write golden model", "implement functional reference", "bitexact reference for RTL verification", or when a Phase 2 C functional reference model is needed for algorithm validation or bandwidth analysis.
This skill should be used when the user asks to "instantiate IP", "generate IP wrapper", "create RTL wrapper for IP", "integrate third-party IP", "wrap IP-XACT descriptor", or when a convention-compliant SV wrapper module is needed for a third-party memory, PLL, PHY, or DSP block.
This skill should be used when the user asks to "generate IP-XACT for this module", "create IEEE 1685 XML descriptor", "produce IP-XACT for EDA tool integration", "IP handoff requires IP-XACT", or when a SoC integration flow needs an IP-XACT component descriptor generated from RTL source.