rtl-agent-team

Read-only architecture review of RTL vs uArch spec with area/timing/power tradeoffs. Use for post-RTL architecture sign-off or suspected spec mismatch.

Builds Phase 3 SystemC TLM-2.0 bus functional models with AMBA (AXI/AHB/APB) support. Use for 'develop BFM', 'SystemC TLM model', 'bus functional model'.

Encoder RD evaluation of C ref model: BD-PSNR/BD-rate (VCEG-M33) across sequences/QPs — 'RD eval', 'BD-rate', codec algorithm quality comparison.

Validate spec contracts across phase boundaries (P3 uarch to P4 RTL to P5 verify): port widths, memory class, REQ traceability. Use at P4/P5 entry.

Internal reference: p1 spec research policy (agent-loaded; do not invoke).

Full 6-phase RTL pipeline from spec to verified design (P1 research through P6 design note). Triggers: 'design a chip', 'full pipeline', 'autopilot'.

Initialize RTL project workspace: directory structure, coding rules, phase guides. Run once per project. Triggers: 'init project', 'new project'.

Plugin diagnostics: version, EDA tool status, state files, hook health. Triggers: 'rat debug', 'plugin status', troubleshooting plugin behavior.

One-time EDA toolchain setup wizard: verify or install tools, build Docker EDA image. Triggers: 'setup tools', 'install tools', 'EDA setup'.

Lint RTL with Verilator, Verible, and slang; report-only quick check for 'run lint', pre-commit, or phase-gate verification (no fixing).

Internal reference: rtl p5s func verify policy (agent-loaded; do not invoke).

P5 Tier 3 module regression: cocotb multi-seed RTL vs reference model with traceability matrix. Triggers 'functional verification', 'regression', 'cocotb test'.

Internal reference: rtl p5s sva policy (agent-loaded; do not invoke).

Internal reference: rtl p7 exploration policy (agent-loaded; do not invoke).

Yosys synthesis estimation on lint-clean RTL — 'synth check', 'area/timing estimate', 'generate SDC'; detects latches, emits DC/Genus-ready SDC.

Generate convention-compliant SV wrapper for third-party IP (memory, PLL, PHY, DSP) — 'instantiate IP', 'IP wrapper', 'integrate third-party IP'.

Generate IEEE 1685-2014 IP-XACT XML descriptor from RTL source — 'generate IP-XACT', IP handoff, or SoC/EDA integration needing component XML.

P5 Tier 4 integration tests: cross-module data flow, reset propagation, boundary handshakes. Triggers 'integration test', 'end-to-end system verification'.

Builds Phase 2 golden C reference model with bitexact conformance and bandwidth estimation. Use for 'build reference model', 'C ref model', 'golden model'.

Reproduce an RTL bug with a minimal TB and isolate root cause via waveform diff — 'reproduce this bug', 'minimal repro TB', regression failure isolation.

Final codec standards compliance gate: bitexact RTL bitstream check against JM/HM reference. Triggers: 'conformance test', 'H.264/H.265 conformance'.

3-way bitexact comparison of C ref model vs SystemC BFM vs RTL on shared vectors; isolates which model drifted. Triggers: 'model consistency', 'model drift'.

P5 coverage closure: prioritizes coverage gaps and generates directed tests. Triggers 'coverage gaps', 'coverage below target', 'uncovered branches'.

Internal reference: rtl p5s integration test policy (agent-loaded; do not invoke).

P5 performance verification: RTL throughput/latency/stalls vs BFM baseline. Triggers 'measure throughput', 'performance regression', 'latency vs BFM'.

P5 UVM verification on commercial simulators (VCS/Questa/Xcelium). Use when UVM methodology or constrained-random sequences/scoreboards are mandated.

Internal reference: rtl p3 uarch policy (agent-loaded; do not invoke).

Internal reference: rtl p5s uvm policy (agent-loaded; do not invoke).

Internal reference: sim tool profiles (agent-loaded; do not invoke).

Evaluate C ref-model decoder against JVET/JCTVC conformance bitstreams (bitexact/MD5) — 'decoder conformance'; C-level, not RTL (rtl-conformance-test).

Internal reference: verification recheck policy (agent-loaded; do not invoke).

Internal reference: rat p4p5 impl verify policy (agent-loaded; do not invoke).

Generate Markdown docs for an RTL module (port/param/FSM tables, synth summary) — 'document this module', 'port table', 'refresh RTL docs'.

Internal reference: ppa optimizer dc policy (agent-loaded; do not invoke).

Internal reference: rat p1p3 spec uarch policy (agent-loaded; do not invoke).

Auto-loop wrapper repeating rtl-ppa-optimize-dc until PPA convergence or plateau. Triggers: 'ultraloop PPA', 'PPA auto-loop', 'optimize PPA until converge'.

Internal RTL routing reference. Defines the single source of truth for Action Skill routing, Action Skill→Orchestrator→Policy mapping, and SessionStart hook export content.

Phase 2 architecture with parallel team workers: dual-stream arch + RefC development. Use for 'arch team', 'Phase 2 team', 'parallel architecture'.

Phase 3 uArch with parallel team workers: dual-stream per-block uArch + BFM development. Use for 'uarch team', 'Phase 3 team', 'parallel uarch'.

Internal reference: rtl p5 verify policy (agent-loaded; do not invoke).