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Generate a C++ Verilator testbench from a module's spec.json, reading the spec from the workspace directory.
Installer avec Codex ou Claude Copiez ce prompt, collez-le dans Codex, Claude ou un autre assistant, puis laissez-le vérifier la page du skill et l'installer pour vous.
Basé sur la classification professionnelle SOC
Run full Chipyard-to-ORFS PnR flow for large designs (SmallBOOM etc.) using All-Mock memory blackboxing in Docker: generate RTL, preprocess nosram, run multi-round ORFS synth->finish with mock SRAMs to avoid OOM.
Docker Chipyard flow: generate RTL from a Chipyard config via Docker, run SRAM mapping, stage artifacts into MyDesign, and hand off to PnR.
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration in Docker: generate RTL from Chipyard Docker, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal PPA.
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration: generate RTL from Chipyard with ENABLE_YOSYS_FLOW, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal PPA.
Unified Chipyard PnR flow: automatically routes to local or Docker workflow based on backend_mode setting.
Unified Chipyard flow: automatically routes to local or Docker workflow based on backend_mode setting.
| name | testbench |
| description | Generate a C++ Verilator testbench from a module's spec.json, reading the spec from the workspace directory. |
| disable-model-invocation | true |
| allowed-tools | ["Read","Write","Bash","Grep","Glob"] |
Generate a C++ Verilator testbench for a hardware module using its spec.json specification.
/chip-agent:testbench <ModuleName>
Extract the module name from $ARGUMENTS. If $ARGUMENTS is empty or blank, ask the user: "Which module should I generate a testbench for? Please provide a PascalCase module name (e.g., ALU, Counter, SimpleRISCV)."
Validate the module name. The name must be PascalCase: first character uppercase, no spaces, no hyphens, only alphanumeric characters. If invalid, inform the user and ask for a corrected name.
Determine the project root directory by finding the nearest ancestor directory of this skill file that contains .claude. Use that directory as the base for all relative paths below.
Read the spec from workspace. Use the Read tool to load:
workspace/<ModuleName>/spec.json
If the file does not exist, STOP and tell the user: "No spec.json found for . Run /chip-agent:requirement-parser first to create a specification."
This step reads spec.json from disk, NOT from conversation context. This ensures the testbench skill works correctly even in a fresh session where no prior conversation about the module exists.
Read the testbench-generator agent definition at agents/testbench-generator.md (relative to the project root). This agent contains the full testbench generation rules, templates, and conventions for both simple and complex (CPU reference model) designs.
Follow the agent's instructions using the spec JSON content to generate a C++ testbench. Apply all rules from the agent definition including:
io_ prefix[TEST N] ... PASS/FAIL and RESULT: PASSED/FAILED X/Y testsWrite the testbench to the workspace path. IMPORTANT: Override the agent's default output path. Write to:
workspace/<ModuleName>/sim/tb_<ModuleName>.cpp
NOT to the agent's flat-mode default of sim/tb_<ModuleName>.cpp. Ensure the directory exists first:
mkdir -p workspace/<ModuleName>/sim
Confirm to the user:
workspace/<ModuleName>/sim/tb_<ModuleName>.cpp/chip-agent:simulate <ModuleName> to compile and execute the testbench."$ARGUMENTS -- A PascalCase module name (e.g., ALU, Counter, SimpleRISCV). The module must have a workspace/<ModuleName>/spec.json file created by /chip-agent:requirement-parser.
workspace/<ModuleName>/sim/tb_<ModuleName>.cpp containing a complete C++ Verilator testbench ready for simulation.