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Cross-model circuit design review with divergence analysis. Sends netlist and rationale to multiple external LLMs for independent audit. Supports minimax-m2.7, qwen-3.6-plus, kimi-k2.5, glm-5.1. Use after analog-design to get independent review before simulation.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
| name | analog-review |
| description | Cross-model circuit design review with divergence analysis. Sends netlist and rationale to multiple external LLMs for independent audit. Supports minimax-m2.7, qwen-3.6-plus, kimi-k2.5, glm-5.1. Use after analog-design to get independent review before simulation. |
Cross-model circuit audit with divergence-focused reporting. After a designer completes a netlist and rationale, this skill sends the raw design files to multiple external LLMs for independent review, then collates their responses into a divergence analysis report.
Divergence over consensus. When reviewers disagree, the disagreement IS the knowledge -- it reveals what is non-obvious about the circuit. The consensus matrix is a summary view; the divergence analysis section is the core of every report. A well-reasoned minority FAIL outweighs a vague majority PASS.
Default behavior on disagreement: flag for human judgment with full reasoning from each reviewer. NOT automatic resolution by vote count.
See shared-references/review-protocol.md for the full review discipline.
Read effort level per shared-references/effort-contract.md. Print at startup:
[effort: <level>] reviewers=<count>
| Effort | Review behavior |
|---|---|
| lite | Skip entirely -- return immediately with "skipped by effort level" |
| standard | 1 model (lowest-latency available) |
| intensive | 2 models, divergence analysis |
| exhaustive | All available models, full divergence report |
Review mode auto-escalation: When the pipeline runs in review mode (no EDA),
cross-model review is the primary quality gate. If the configured effort is lite
or standard, it is automatically escalated to intensive (2 models + divergence
analysis). This ensures at least one independent audit when simulation is unavailable.
| Name | Provider | Model ID |
|---|---|---|
| minimax | minimax | minimax-m2.7 |
| qwen | openai-compatible | qwen-3.6-plus |
| kimi | openai-compatible | kimi-k2.5 |
| glm | openai-compatible | glm-5.1 |
Copy config/reviewers.example.yml to config/reviewers.yml and fill in API
keys. config/reviewers.yml is gitignored.
# config/reviewers.example.yml (abbreviated)
reviewers:
minimax:
model: minimax-m2.7
api_key: "${MINIMAX_API_KEY}"
base_url: "https://api.minimax.chat/v1"
timeout: 120
qwen:
model: qwen-3.6-plus
api_key: "${QWEN_API_KEY}"
base_url: "https://dashscope.aliyuncs.com/compatible-mode/v1"
timeout: 120
kimi:
model: kimi-k2.5
api_key: "${KIMI_API_KEY}"
base_url: "https://api.moonshot.cn/v1"
timeout: 120
glm:
model: glm-5.1
api_key: "${GLM_API_KEY}"
base_url: "https://open.bigmodel.cn/api/paas/v4"
timeout: 120
voting:
min_reviewers: 2
tie_break: "flag_for_human"
/analog-review checkVerify all reviewer connectivity. Sends a lightweight probe to each configured reviewer and reports status and latency.
python3 tools/review_bridge.py check --config config/reviewers.yml
Example output:
minimax (minimax-m2.7) ok 1.2s
qwen (qwen-3.6-plus) ok 0.8s
kimi (kimi-k2.5) FAIL 401 Unauthorized
glm (glm-5.1) ok 1.5s
Available: 3/4 -- meets min_reviewers (2)
/analog-review run <block-path>Execute a cross-model review for the specified block.
circuit/<block>.scs -- netlistcircuit/rationale.md -- design rationalespec.yml -- target specificationswiki/anti-patterns/ matching the current
topology tags. This is the ONLY wiki content injected into the review prompt.verifier-reports/cross-model-review.md.python3 tools/review_bridge.py review \
--netlist circuit/<block>.scs \
--rationale circuit/rationale.md \
--spec spec.yml \
--effort <level>
/analog-review reportDisplay the most recent verifier-reports/cross-model-review.md.
Sent identically to every external model. Contains ONLY raw files -- no agent self-assessments, prior review results, or designer confidence statements (reviewer independence).
You are an analog IC design review expert. Review the following circuit netlist
and design rationale.
## Circuit Netlist
{netlist_content}
## Design Rationale
{rationale_content}
## Target Specifications
{spec_yml_content}
## Known Risks for This Topology (from knowledge base)
{wiki_anti_patterns_if_any}
Evaluate on these dimensions, giving PASS / WARN / FAIL for each:
1. **Connection correctness**: dangling nodes, pin mismatches, bulk errors
2. **Bias soundness**: mirror ratios, gm/Id range, headroom margins
3. **Sizing consistency**: do rationale equations match actual parameters?
4. **Topology risks**: known traps (CMFB polarity, compensation, etc.)
5. **Spec achievability**: can these specs be met with the given sizing?
For each WARN/FAIL: describe the problem, its impact, and a suggested fix.
Each reviewer evaluates 5 dimensions with PASS / WARN / FAIL:
Output to verifier-reports/cross-model-review.md:
[DIVERGENCE] or [CONSENSUS]When reviewers disagree, default behavior is flag for human judgment with full reasoning from each side -- not automatic resolution by vote count.
If wiki/anti-patterns/ contains entries tagged with the current topology,
those entries are appended to the review prompt under "Known Risks for This
Topology." This is the only wiki content that enters the review prompt.
The review prompt contains ONLY raw file contents:
NEVER include: agent self-assessments, prior review results, designer confidence statements, or any interpretation of the design. Each reviewer must form its own judgment from raw materials.
This skill can be used independently -- it does not require /analog-pipeline.
Given the input files (netlist, rationale, spec), it runs a complete review cycle.
SOC 職業分類に基づく
Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have the worst coupling?", "where does settling bottleneck?" — by parsing the netlist, building a sparse graph, and solving the resistance Laplacian / summing the capacitance network. Format-agnostic: Calibre xRC mr_pp (.pex.netlist), Spectre flat, Spectre with subckt + include chain (.pex / .pxi splits), and Cadence calibreview bundles all produce identical kernel output. TRIGGER whenever the user shares a post-layout / extracted / parasitic netlist and asks about symmetry, parasitic C, parasitic R, coupling, driving-point resistance, within-net R distribution, pin-to-pin R, SAR CDAC analysis, comparator input impedance — even if they don't say "post-layout". Also trigger on filenames ending in .pex.netlist, .pxi, or mentions of xRC, Calibre extraction, RCC m
ADC characterization orchestrator in the analog-agents project. Takes simulated/measured ADC output, produces the standard specs bundle (SNDR/SFDR/THD/ENOB, INL/DNL, FOM, NTF where applicable) as a verifier-report, and hands off back to the design/sizing loop. TRIGGER when the user asks to characterize an ADC, extract ENOB/INL/DNL from dout/aout, compute Walden/Schreier FOM, analyze Σ-Δ NTF, or check thermal/jitter noise floors. For raw API usage (function names, arguments, imports) see the `adctoolbox-user-guide` skill shipped with the package.
Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.
Move, clone, package, archive, split, or reorganize Cadence Virtuoso cells and libraries at the design-data level. Use this skill whenever the user wants to: copy a TB to another library, reproduce a sim independently in a fresh library, hand off a design, prepare a tapeout archive, split one TB cell into several, promote a block between libraries, or enumerate a design's full reference hierarchy. Think of it as the "librarian" for your Virtuoso workspace — it knows which cells belong together, how to move them without breaking config bindings, and how to distinguish project cells from PDK / std-cell / analogLib references.
Self-evolution engine for analog-agents. Reviews completed design sessions to extract lessons, discover new anti-patterns, propose checklist additions, and refine agent prompts. Run after design convergence or project completion. TRIGGER on: "evolve", "what did we learn", "improve skills", "meta-review", "self-improve", or automatically at end of analog-pipeline.
MANDATORY — MUST load this skill when the user mentions: OTA, ADC, PLL, comparator, bandgap, LDO, amplifier, opamp, or any analog/mixed-signal IC design task. Full analog design pipeline: spec -> architecture -> design -> verify -> deliver. Orchestrates analog-decompose, analog-behavioral, analog-design, analog-review, analog-verify, analog-integrate, and analog-wiki skills.
